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42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Thu, 19 Nov 2020 17:43:09 +0200
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Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be
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exported and referenced in DT
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Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
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from phandle in DT.
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Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/sama7g5.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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--- a/drivers/clk/at91/sama7g5.c
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+++ b/drivers/clk/at91/sama7g5.c
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@@ -117,7 +117,8 @@ static const struct {
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.p = "cpupll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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- .c = 1, },
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+ .c = 1,
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+ .eid = PMC_CPUPLL, },
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},
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[PLL_ID_SYS] = {
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@@ -131,7 +132,8 @@ static const struct {
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.p = "syspll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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- .c = 1, },
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+ .c = 1,
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+ .eid = PMC_SYSPLL, },
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},
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[PLL_ID_DDR] = {
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