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fb2c6e9d4d
Removed because they are upstream: generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=c5c0760adc260d55265c086b9efb350ea6dda38b generic/pending-5.15/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=448cc8b5f743985f6d1d98aa4efb386fef4c3bf2 generic/pending-5.15/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=9fcadd125044007351905d40c405fadc2d3bb6d6 Add new configuration symbols for tegra target. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
77 lines
2.5 KiB
Diff
77 lines
2.5 KiB
Diff
From c0a440031d4314d1023c1b87f43a4233634eebdb Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Sun, 19 Mar 2023 12:57:15 +0000
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Subject: [PATCH] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Set MDIO bus clock frequency and allow setting a custom maximum
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frequency from device tree.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Tested-by: Bjørn Mork <bjorn@mork.no>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 21 +++++++++++++++++++++
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 +++++++
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2 files changed, 28 insertions(+)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -701,8 +701,10 @@ static const struct phylink_mac_ops mtk_
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static int mtk_mdio_init(struct mtk_eth *eth)
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{
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+ unsigned int max_clk = 2500000, divider;
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struct device_node *mii_np;
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int ret;
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+ u32 val;
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mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
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if (!mii_np) {
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@@ -728,6 +730,25 @@ static int mtk_mdio_init(struct mtk_eth
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eth->mii_bus->parent = eth->dev;
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snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
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+
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+ if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
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+ if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
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+ dev_err(eth->dev, "MDIO clock frequency out of range");
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+ ret = -EINVAL;
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+ goto err_put_node;
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+ }
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+ max_clk = val;
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+ }
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+ divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
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+
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+ /* Configure MDC Divider */
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+ val = mtk_r32(eth, MTK_PPSC);
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+ val &= ~PPSC_MDC_CFG;
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+ val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
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+ mtk_w32(eth, val, MTK_PPSC);
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+
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+ dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
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+
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ret = of_mdiobus_register(eth->mii_bus, mii_np);
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err_put_node:
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -363,6 +363,13 @@
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#define RX_DMA_VTAG_V2 BIT(0)
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#define RX_DMA_L4_VALID_V2 BIT(2)
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+/* PHY Polling and SMI Master Control registers */
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+#define MTK_PPSC 0x10000
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+#define PPSC_MDC_CFG GENMASK(29, 24)
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+#define PPSC_MDC_TURBO BIT(20)
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+#define MDC_MAX_FREQ 25000000
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+#define MDC_MAX_DIVIDER 63
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+
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/* PHY Indirect Access Control registers */
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#define MTK_PHY_IAC 0x10004
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#define PHY_IAC_ACCESS BIT(31)
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