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88bf652525
Reorganize dtsi patches with upstream version and drop dtsi in 5.15 files. Also add an additional upstream patch for hwspinlock support. Refresh all the dts with needed changes. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
102 lines
2.5 KiB
Diff
102 lines
2.5 KiB
Diff
From 4af1defb305798d1a064a5ea0d0c9b30e5eee185 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 7 Jul 2022 03:09:35 +0200
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Subject: [PATCH 1/8] ARM: dts: qcom: ipq8064: add multiple missing pin
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definition
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Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
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pins and rgmii2 pins for ipq8064.
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Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064
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dtsi.
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Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to
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ipq8064 dtsi.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Tested-by: Jonathan McDowell <noodles@earth.li>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220707010943.20857-2-ansuelsmth@gmail.com
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -----
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arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 -------
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++
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3 files changed, 32 insertions(+), 15 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
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@@ -305,15 +305,6 @@
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};
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};
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- mdio0_pins: mdio0_pins {
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- mux {
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- pins = "gpio0", "gpio1";
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- function = "gpio";
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- drive-strength = <8>;
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- bias-disable;
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- };
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- };
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-
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mdio1_pins: mdio1_pins {
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mux {
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pins = "gpio10", "gpio11";
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -382,6 +382,13 @@
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};
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};
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+ i2c4_pins: i2c4-default {
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+ pins = "gpio12", "gpio13";
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+ function = "gsbi4";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -424,6 +431,8 @@
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pullups {
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pins = "gpio39";
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+ function = "nand";
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+ drive-strength = <10>;
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bias-pull-up;
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};
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@@ -431,9 +440,32 @@
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pins = "gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47";
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+ function = "nand";
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+ drive-strength = <10>;
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bias-bus-hold;
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};
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};
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+
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+ mdio0_pins: mdio0-pins {
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+ mux {
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+ pins = "gpio0", "gpio1";
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+ function = "mdio";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+
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+ rgmii2_pins: rgmii2-pins {
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+ mux {
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+ pins = "gpio27", "gpio28", "gpio29",
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+ "gpio30", "gpio31", "gpio32",
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+ "gpio51", "gpio52", "gpio59",
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+ "gpio60", "gpio61", "gpio62";
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+ function = "rgmii2";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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};
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intc: interrupt-controller@2000000 {
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