mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
147 lines
4.3 KiB
Diff
147 lines
4.3 KiB
Diff
From 9796f3807764567ecde6e3787a66e4b4edbc35df Mon Sep 17 00:00:00 2001
|
|
From: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
Date: Fri, 22 Jul 2016 11:40:13 -0400
|
|
Subject: [PATCH] rtl8xxxu: Implement rtl8188eu_config_channel()
|
|
|
|
The 8188eu doesn't seem to have REG_FPGA0_ANALOG2, so implement it's
|
|
own specific version.
|
|
|
|
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
---
|
|
.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 117 +++++++++++++++++++++
|
|
1 file changed, 117 insertions(+)
|
|
|
|
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
|
|
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
|
|
@@ -283,6 +283,122 @@ static struct rtl8xxxu_rfregval rtl8188e
|
|
{0xff, 0xffffffff}
|
|
};
|
|
|
|
+void rtl8188eu_config_channel(struct ieee80211_hw *hw)
|
|
+{
|
|
+ struct rtl8xxxu_priv *priv = hw->priv;
|
|
+ u32 val32, rsr;
|
|
+ u8 val8, opmode;
|
|
+ bool ht = true;
|
|
+ int sec_ch_above, channel;
|
|
+ int i;
|
|
+
|
|
+ opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
|
|
+ rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
|
|
+ channel = hw->conf.chandef.chan->hw_value;
|
|
+
|
|
+ switch (hw->conf.chandef.width) {
|
|
+ case NL80211_CHAN_WIDTH_20_NOHT:
|
|
+ ht = false;
|
|
+ case NL80211_CHAN_WIDTH_20:
|
|
+ opmode |= BW_OPMODE_20MHZ;
|
|
+ rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
|
|
+
|
|
+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
|
|
+ val32 &= ~FPGA_RF_MODE;
|
|
+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
|
|
+
|
|
+ val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
|
|
+ val32 &= ~FPGA_RF_MODE;
|
|
+ rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
|
|
+ break;
|
|
+ case NL80211_CHAN_WIDTH_40:
|
|
+ if (hw->conf.chandef.center_freq1 >
|
|
+ hw->conf.chandef.chan->center_freq) {
|
|
+ sec_ch_above = 1;
|
|
+ channel += 2;
|
|
+ } else {
|
|
+ sec_ch_above = 0;
|
|
+ channel -= 2;
|
|
+ }
|
|
+
|
|
+ opmode &= ~BW_OPMODE_20MHZ;
|
|
+ rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
|
|
+ rsr &= ~RSR_RSC_BANDWIDTH_40M;
|
|
+ if (sec_ch_above)
|
|
+ rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
|
|
+ else
|
|
+ rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
|
|
+ rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
|
|
+
|
|
+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
|
|
+ val32 |= FPGA_RF_MODE;
|
|
+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
|
|
+
|
|
+ val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
|
|
+ val32 |= FPGA_RF_MODE;
|
|
+ rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
|
|
+
|
|
+ /*
|
|
+ * Set Control channel to upper or lower. These settings
|
|
+ * are required only for 40MHz
|
|
+ */
|
|
+ val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
|
|
+ val32 &= ~CCK0_SIDEBAND;
|
|
+ if (!sec_ch_above)
|
|
+ val32 |= CCK0_SIDEBAND;
|
|
+ rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
|
|
+
|
|
+ val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
|
|
+ val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
|
|
+ if (sec_ch_above)
|
|
+ val32 |= OFDM_LSTF_PRIME_CH_LOW;
|
|
+ else
|
|
+ val32 |= OFDM_LSTF_PRIME_CH_HIGH;
|
|
+ rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
|
|
+
|
|
+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
|
|
+ val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
|
|
+ if (sec_ch_above)
|
|
+ val32 |= FPGA0_PS_UPPER_CHANNEL;
|
|
+ else
|
|
+ val32 |= FPGA0_PS_LOWER_CHANNEL;
|
|
+ rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ for (i = RF_A; i < priv->rf_paths; i++) {
|
|
+ val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
|
|
+ val32 &= ~MODE_AG_CHANNEL_MASK;
|
|
+ val32 |= channel;
|
|
+ rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
|
|
+ }
|
|
+
|
|
+ if (ht)
|
|
+ val8 = 0x0e;
|
|
+ else
|
|
+ val8 = 0x0a;
|
|
+
|
|
+#if 0
|
|
+ rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
|
|
+ rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
|
|
+
|
|
+ rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
|
|
+ rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
|
|
+#endif
|
|
+
|
|
+ for (i = RF_A; i < priv->rf_paths; i++) {
|
|
+ val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
|
|
+ if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
|
|
+ val32 &= ~MODE_AG_CHANNEL_20MHZ;
|
|
+ else
|
|
+ val32 |= MODE_AG_CHANNEL_20MHZ;
|
|
+ rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
|
|
+ }
|
|
+}
|
|
+
|
|
static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv)
|
|
{
|
|
struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu;
|
|
@@ -1009,6 +1125,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
|
|
.init_phy_bb = rtl8188eu_init_phy_bb,
|
|
.init_phy_rf = rtl8188eu_init_phy_rf,
|
|
.phy_iq_calibrate = rtl8188eu_phy_iq_calibrate,
|
|
+ .config_channel = rtl8188eu_config_channel,
|
|
.parse_rx_desc = rtl8xxxu_parse_rxdesc16,
|
|
.usb_quirks = rtl8188e_usb_quirks,
|
|
.writeN_block_size = 128,
|