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9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
60 lines
2.4 KiB
Diff
60 lines
2.4 KiB
Diff
From 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Tue, 30 Nov 2021 18:29:06 +0100
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Subject: [PATCH] PCI: aardvark: Clear all MSIs at setup
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).
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Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,
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to ensure that we don't start receiving spurious interrupts.
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Use this new mask in advk_pcie_handle_msi();
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Link: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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---
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drivers/pci/controller/pci-aardvark.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -114,6 +114,7 @@
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
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#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
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+#define PCIE_MSI_ALL_MASK GENMASK(31, 0)
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#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
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#define PCIE_MSI_DATA_MASK GENMASK(15, 0)
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@@ -577,6 +578,7 @@ static void advk_pcie_setup_hw(struct ad
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advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
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/* Clear all interrupts */
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+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
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advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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@@ -589,7 +591,7 @@ static void advk_pcie_setup_hw(struct ad
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
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/* Unmask all MSIs */
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- advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
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+ advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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/* Enable summary interrupt for GIC SPI source */
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reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
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@@ -1399,7 +1401,7 @@ static void advk_pcie_handle_msi(struct
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msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
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msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
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- msi_status = msi_val & ~msi_mask;
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+ msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
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for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
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if (!(BIT(msi_idx) & msi_status))
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