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793f8ab62c
Add kernel patches for version 6.1. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
155 lines
5.1 KiB
Diff
155 lines
5.1 KiB
Diff
From 4db71468da38668b1b2b5ad3d8bf120f702b6387 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Thu, 25 May 2023 17:04:20 +0100
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Subject: [PATCH] bcm2835-dma: Fixes for dma_abort
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There is a problem with the current abort scheme
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when dma is blocked on a DREQ which prevents halting.
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This is triggered by SPI driver which aborts dma
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in this state and so leads to a halt timeout.
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Discussion with Broadcom suggests the sequence:
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CS.ACTIVE=0
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while (CS.OUTSTANDING_TRANSACTIONS == 0)
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wait()
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DEBUG.RESET=1
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should be safe on a dma40 channel.
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Unfortunately the non-dma40 channels don't have
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OUTSTANDING_TRANSACTIONS, so we need a more
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complicated scheme.
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We attempt to abort the channel, which will work
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if there is no blocked DREQ.
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It it times out, we can assume there is no AXI
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transfer in progress and reset anyway.
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The length of the timeout is observed at ~20us.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/dma/bcm2835-dma.c | 74 +++++++++++++++++++++------------------
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1 file changed, 40 insertions(+), 34 deletions(-)
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--- a/drivers/dma/bcm2835-dma.c
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+++ b/drivers/dma/bcm2835-dma.c
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@@ -245,6 +245,7 @@ struct bcm2835_desc {
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#define BCM2711_DMA40_ERR BIT(10)
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#define BCM2711_DMA40_QOS(x) (((x) & 0x1f) << 16)
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#define BCM2711_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20)
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+#define BCM2711_DMA40_TRANSACTIONS BIT(25)
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#define BCM2711_DMA40_WAIT_FOR_WRITES BIT(28)
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#define BCM2711_DMA40_DISDEBUG BIT(29)
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#define BCM2711_DMA40_ABORT BIT(30)
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@@ -663,30 +664,37 @@ static void bcm2835_dma_fill_cb_chain_wi
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static void bcm2835_dma_abort(struct bcm2835_chan *c)
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{
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void __iomem *chan_base = c->chan_base;
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- long int timeout = 10000;
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-
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- /*
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- * A zero control block address means the channel is idle.
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- * (The ACTIVE flag in the CS register is not a reliable indicator.)
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- */
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- if (!readl(chan_base + BCM2835_DMA_ADDR))
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- return;
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+ long timeout = 100;
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if (c->is_40bit_channel) {
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- /* Halt the current DMA */
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- writel(readl(chan_base + BCM2711_DMA40_CS) | BCM2711_DMA40_HALT,
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+ /*
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+ * A zero control block address means the channel is idle.
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+ * (The ACTIVE flag in the CS register is not a reliable indicator.)
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+ */
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+ if (!readl(chan_base + BCM2711_DMA40_CB))
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+ return;
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+
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+ /* Pause the current DMA */
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+ writel(readl(chan_base + BCM2711_DMA40_CS) & ~BCM2711_DMA40_ACTIVE,
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chan_base + BCM2711_DMA40_CS);
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- while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_HALT) && --timeout)
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+ /* wait for outstanding transactions to complete */
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+ while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_TRANSACTIONS) &&
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+ --timeout)
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cpu_relax();
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- /* Peripheral might be stuck and fail to halt */
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+ /* Peripheral might be stuck and fail to complete */
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if (!timeout)
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dev_err(c->vc.chan.device->dev,
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- "failed to halt dma\n");
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+ "failed to complete pause on dma %d (CS:%08x)\n", c->ch,
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+ readl(chan_base + BCM2711_DMA40_CS));
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+ /* Set CS back to default state */
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writel(BCM2711_DMA40_PROT, chan_base + BCM2711_DMA40_CS);
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- writel(0, chan_base + BCM2711_DMA40_CB);
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+
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+ /* Reset the DMA */
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+ writel(readl(chan_base + BCM2711_DMA40_DEBUG) | BCM2711_DMA40_DEBUG_RESET,
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+ chan_base + BCM2711_DMA40_DEBUG);
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} else {
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/*
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* A zero control block address means the channel is idle.
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@@ -695,36 +703,34 @@ static void bcm2835_dma_abort(struct bcm
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if (!readl(chan_base + BCM2835_DMA_ADDR))
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return;
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- /* Write 0 to the active bit - Pause the DMA */
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- writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE,
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- chan_base + BCM2835_DMA_CS);
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-
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- /* wait for DMA to be paused */
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- while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_WAITING_FOR_WRITES)
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- && --timeout)
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- cpu_relax();
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-
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- /* Peripheral might be stuck and fail to signal AXI write responses */
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- if (!timeout)
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- dev_err(c->vc.chan.device->dev,
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- "failed to pause dma\n");
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-
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/* We need to clear the next DMA block pending */
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writel(0, chan_base + BCM2835_DMA_NEXTCB);
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/* Abort the DMA, which needs to be enabled to complete */
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writel(readl(chan_base + BCM2835_DMA_CS) | BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
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- chan_base + BCM2835_DMA_CS);
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+ chan_base + BCM2835_DMA_CS);
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- /* wait for DMA to have been aborted */
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- timeout = 10000;
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+ /* wait for DMA to be aborted */
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while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_ABORT) && --timeout)
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cpu_relax();
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- /* Peripheral might be stuck and fail to signal AXI write responses */
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- if (!timeout)
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+ /* Write 0 to the active bit - Pause the DMA */
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+ writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE,
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+ chan_base + BCM2835_DMA_CS);
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+
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+ /*
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+ * Peripheral might be stuck and fail to complete
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+ * This is expected when dreqs are enabled but not asserted
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+ * so only report error in non dreq case
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+ */
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+ if (!timeout && !(readl(chan_base + BCM2835_DMA_TI) &
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+ (BCM2835_DMA_S_DREQ | BCM2835_DMA_D_DREQ)))
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dev_err(c->vc.chan.device->dev,
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- "failed to abort dma\n");
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+ "failed to complete pause on dma %d (CS:%08x)\n", c->ch,
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+ readl(chan_base + BCM2835_DMA_CS));
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+
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+ /* Set CS back to default state and reset the DMA */
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+ writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS);
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}
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}
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