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f49d4aebe2
CONFIG_FORTIFY_SOURCE=y is already set in the generic kernel
configuration, but it is not working for MIPS on kernel 5.4, support for
MIPS was only added with kernel 5.5, other architectures like aarch64
support FORTIFY_SOURCE already since some time.
This patch adds support for FORTIFY_SOURCE to MIPS with kernel 5.4,
kernel 5.10 already supports this and needs no changes.
This backports one patch from kernel 5.5 and one fix from 5.8 to make
fortify source also work on our kernel 5.4.
The changes are not compatible with the
306-mips_mem_functions_performance.patch patch which was also removed
with kernel 5.10, probably because of the same problems. I think it is
not needed anyway as the compiler should automatically optimize the
calls to memset(), memcpy() and memmove() even when not explicitly
telling the compiler to use the build in variant.
This increases the size of an uncompressed kernel by less than 1 KB.
Acked-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 9ffa2f8193)
126 lines
4.1 KiB
Diff
126 lines
4.1 KiB
Diff
From b5a52351a66f3c2a7a207548aa87d78ff2d336c0 Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Wed, 10 Jul 2019 00:24:48 +0800
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Subject: [PATCH] MIPS: ralink: mt7621: add memory detection support
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mt7621 has the following memory map:
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0x0-0x1c000000: lower 448m memory
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0x1c000000-0x2000000: peripheral registers
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0x20000000-0x2400000: higher 64m memory
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detect_memory_region in arch/mips/kernel/setup.c only add the first
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memory region and isn't suitable for 512m memory detection because
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it may accidentally read the memory area for peripheral registers.
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This commit adds memory detection capability for mt7621:
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1. add the highmem area when 512m is detected.
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2. guard memcmp from accessing peripheral registers:
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This only happens when some weird user decided to change
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kernel load address to 256m or higher address. Since this
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is a quite unusual case, we just skip 512m testing and return
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256m as memory size.
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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---
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arch/mips/include/asm/mach-ralink/mt7621.h | 7 ++---
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arch/mips/ralink/mt7621.c | 30 +++++++++++++++++++---
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2 files changed, 30 insertions(+), 7 deletions(-)
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--- a/arch/mips/include/asm/mach-ralink/mt7621.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
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@@ -44,9 +44,10 @@
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#define CPU_PLL_FBDIV_MASK 0x7f
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#define CPU_PLL_FBDIV_SHIFT 4
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-#define MT7621_DRAM_BASE 0x0
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-#define MT7621_DDR2_SIZE_MIN 32
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-#define MT7621_DDR2_SIZE_MAX 256
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+#define MT7621_LOWMEM_BASE 0x0
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+#define MT7621_LOWMEM_MAX_SIZE 0x1C000000
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+#define MT7621_HIGHMEM_BASE 0x20000000
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+#define MT7621_HIGHMEM_SIZE 0x4000000
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#define MT7621_CHIP_NAME0 0x3637544D
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#define MT7621_CHIP_NAME1 0x20203132
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -13,6 +13,7 @@
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#include <linux/clk-provider.h>
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#include <dt-bindings/clock/mt7621-clk.h>
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+#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-ops.h>
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#include <asm/mips-cps.h>
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@@ -55,6 +56,8 @@
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#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
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#define MT7621_GPIO_MODE_SDHCI_GPIO 1
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+static void *detect_magic __initdata = detect_memory_region;
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+
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static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
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static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
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static struct rt2880_pmx_func uart3_grp[] = {
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@@ -139,6 +142,28 @@ static struct clk *__init mt7621_add_sys
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return clk;
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}
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+void __init mt7621_memory_detect(void)
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+{
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+ void *dm = &detect_magic;
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+ phys_addr_t size;
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+
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+ for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
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+ if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))
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+ break;
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+ }
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+
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+ if ((size == 256 * SZ_1M) &&
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+ (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
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+ __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {
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+ add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE,
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+ BOOT_MEM_RAM);
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+ add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE,
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+ BOOT_MEM_RAM);
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+ } else {
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+ add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM);
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+ }
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+}
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+
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void __init ralink_clk_init(void)
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{
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u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
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@@ -317,10 +342,7 @@ void prom_soc_init(struct ralink_soc_inf
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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- soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
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- soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
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- soc_info->mem_base = MT7621_DRAM_BASE;
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-
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+ soc_info->mem_detect = mt7621_memory_detect;
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rt2880_pinmux_data = mt7621_pinmux_data;
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--- a/arch/mips/ralink/common.h
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+++ b/arch/mips/ralink/common.h
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@@ -17,6 +17,7 @@ struct ralink_soc_info {
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unsigned long mem_size;
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unsigned long mem_size_min;
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unsigned long mem_size_max;
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+ void (*mem_detect)(void);
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};
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extern struct ralink_soc_info soc_info;
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--- a/arch/mips/ralink/of.c
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+++ b/arch/mips/ralink/of.c
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@@ -87,6 +87,8 @@ void __init plat_mem_setup(void)
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of_scan_flat_dt(early_init_dt_find_memory, NULL);
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if (memory_dtb)
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of_scan_flat_dt(early_init_dt_scan_memory, NULL);
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+ else if (soc_info.mem_detect)
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+ soc_info.mem_detect();
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else if (soc_info.mem_size)
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add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
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BOOT_MEM_RAM);
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