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0171157d45
The patches were generated from the RPi repo with the following command: git format-patch v6.6.44..rpi-6.6.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
100 lines
3.7 KiB
Diff
100 lines
3.7 KiB
Diff
From b6b4260fa546d1dc7421c7cfed059052dae04227 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Thu, 18 Jul 2024 09:40:03 +0100
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Subject: [PATCH 1197/1215] sound/soc: dwc-i2s: choose FIFO thresholds based on
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DMA burst constraints
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Valid ranges for the I2S peripheral's FIFO configuration include a depth
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of 16 - unconditionally setting the burst length to 16 with a fifo
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threshold of size/2 will cause under/overflows.
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For DMA engines with restricted capabilities the requested burst length
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and FIFO thresholds need to be adjusted downward accordingly.
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Both the RX and TX FIFOs operate on "less-than" thresholds. Setting the
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TX threshold to fifo_size minus burst means the FIFO is kept nearly-full.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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sound/soc/dwc/dwc-i2s.c | 21 ++++++++++++++++-----
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sound/soc/dwc/local.h | 1 +
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2 files changed, 17 insertions(+), 5 deletions(-)
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--- a/sound/soc/dwc/dwc-i2s.c
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+++ b/sound/soc/dwc/dwc-i2s.c
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@@ -236,6 +236,8 @@ static void dw_i2s_config(struct dw_i2s_
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u32 ch_reg;
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struct i2s_clk_config_data *config = &dev->config;
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u32 dmacr;
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+ u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
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+ u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
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i2s_disable_channels(dev, stream);
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@@ -251,7 +253,7 @@ static void dw_i2s_config(struct dw_i2s_
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i2s_write_reg(dev->i2s_base, TCR(ch_reg),
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dev->xfer_resolution);
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i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
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- dev->fifo_th - 1);
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+ fifo_depth - dev->fifo_th - 1);
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i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |
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dev->tdm_mask << TER_TXSLOT_SHIFT);
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dmacr |= (DMACR_DMAEN_TXCH0 << ch_reg);
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@@ -783,8 +785,8 @@ static int dw_configure_dai_by_pd(struct
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dev->capture_dma_data.pd.data = pdata->capture_dma_data;
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dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
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dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
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- dev->play_dma_data.pd.max_burst = 16;
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- dev->capture_dma_data.pd.max_burst = 16;
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+ dev->play_dma_data.pd.max_burst = dev->fifo_th;
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+ dev->capture_dma_data.pd.max_burst = dev->fifo_th;
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dev->play_dma_data.pd.addr_width = bus_widths[idx];
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dev->capture_dma_data.pd.addr_width = bus_widths[idx];
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dev->play_dma_data.pd.filter = pdata->filter;
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@@ -815,7 +817,10 @@ static int dw_configure_dai_by_dt(struct
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dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
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dev->play_dma_data.dt.fifo_size = fifo_depth *
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(fifo_width[idx2]) >> 8;
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- dev->play_dma_data.dt.maxburst = 16;
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+ if (dev->max_dma_burst)
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+ dev->play_dma_data.dt.maxburst = dev->max_dma_burst;
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+ else
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+ dev->play_dma_data.dt.maxburst = fifo_depth / 2;
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}
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if (COMP1_RX_ENABLED(comp1)) {
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idx2 = COMP2_RX_WORDSIZE_0(comp2);
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@@ -824,9 +829,14 @@ static int dw_configure_dai_by_dt(struct
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dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
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dev->capture_dma_data.dt.fifo_size = fifo_depth *
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(fifo_width[idx2] >> 8);
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- dev->capture_dma_data.dt.maxburst = 16;
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+ if (dev->max_dma_burst)
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+ dev->capture_dma_data.dt.maxburst = dev->max_dma_burst;
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+ else
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+ dev->capture_dma_data.dt.maxburst = fifo_depth / 2;
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}
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+ if (dev->max_dma_burst)
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+ dev->fifo_th = min(dev->max_dma_burst, dev->fifo_th);
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return 0;
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}
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@@ -1070,6 +1080,7 @@ static int dw_i2s_probe(struct platform_
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}
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}
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+ of_property_read_u32(pdev->dev.of_node, "dma-maxburst", &dev->max_dma_burst);
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dev->bclk_ratio = 0;
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dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
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dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
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--- a/sound/soc/dwc/local.h
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+++ b/sound/soc/dwc/local.h
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@@ -133,6 +133,7 @@ struct dw_i2s_dev {
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u32 ccr;
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u32 xfer_resolution;
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u32 fifo_th;
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+ u32 max_dma_burst;
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u32 l_reg;
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u32 r_reg;
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bool is_jh7110; /* Flag for StarFive JH7110 SoC */
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