mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
f953a1a4bf
The 2.4GHz interface doesn't come up properly with the log showing: mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) As seen on other MT7621 boards this is caused by a missing reset GPIO. The MT7621 dtsi set GPIO 19 as PCIe reset GPIO, which on this board reset the 5GHz interface on port 0. Add GPIO 8 to the PCIe reset GPIO list to also reset the 2.4GHz interface on port 1. Signed-off-by: Alban Bedel <albeu@free.fr>
169 lines
2.5 KiB
Plaintext
169 lines
2.5 KiB
Plaintext
#include "mt7621.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
compatible = "zbtlink,zbt-wg2626", "mediatek,mt7621-soc";
|
|
model = "Zbtlink ZBT-WG2626";
|
|
|
|
aliases {
|
|
led-boot = &led_status;
|
|
led-failsafe = &led_status;
|
|
led-running = &led_status;
|
|
led-upgrade = &led_status;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,115200";
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_status: status {
|
|
label = "green:status";
|
|
gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c {
|
|
status = "okay";
|
|
};
|
|
|
|
&sdhci {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <10000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x0 0x30000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@30000 {
|
|
label = "u-boot-env";
|
|
reg = <0x30000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
factory: partition@40000 {
|
|
label = "factory";
|
|
reg = <0x40000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@50000 {
|
|
compatible = "denx,uimage";
|
|
label = "firmware";
|
|
reg = <0x50000 0xfb0000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
|
|
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
|
|
<&gpio 8 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
&pcie0 {
|
|
mt76@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x8000>;
|
|
ieee80211-freq-limit = <5000000 6000000>;
|
|
};
|
|
};
|
|
|
|
&pcie1 {
|
|
mt76@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x0000>;
|
|
ieee80211-freq-limit = <2400000 2500000>;
|
|
};
|
|
};
|
|
|
|
ðernet {
|
|
pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;
|
|
};
|
|
|
|
&gmac0 {
|
|
nvmem-cells = <&macaddr_factory_e000>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&switch0 {
|
|
ports {
|
|
port@0 {
|
|
status = "okay";
|
|
label = "lan1";
|
|
};
|
|
|
|
port@1 {
|
|
status = "okay";
|
|
label = "lan2";
|
|
};
|
|
|
|
port@2 {
|
|
status = "okay";
|
|
label = "lan3";
|
|
};
|
|
|
|
port@3 {
|
|
status = "okay";
|
|
label = "lan4";
|
|
};
|
|
|
|
port@4 {
|
|
status = "okay";
|
|
label = "wan";
|
|
nvmem-cells = <&macaddr_factory_e000>;
|
|
nvmem-cell-names = "mac-address";
|
|
mac-address-increment = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&state_default {
|
|
gpio {
|
|
groups = "wdt", "rgmii2";
|
|
function = "gpio";
|
|
};
|
|
};
|
|
|
|
&factory {
|
|
compatible = "nvmem-cells";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
macaddr_factory_e000: macaddr@e000 {
|
|
reg = <0xe000 0x6>;
|
|
};
|
|
};
|