mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 23:42:43 +00:00
33 lines
957 B
Diff
33 lines
957 B
Diff
From f0571ab140723f9a898d4a404118580534dcc468 Mon Sep 17 00:00:00 2001
|
|
From: Chen-Yu Tsai <wens@csie.org>
|
|
Date: Sat, 5 Dec 2015 21:16:47 +0800
|
|
Subject: [PATCH] ARM: dts: sun7i: Add VE (Video Engine) module clock node
|
|
|
|
The video engine has its own module clock, which also includes a
|
|
reset control for it.
|
|
|
|
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
---
|
|
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
|
|
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
|
|
@@ -527,6 +527,15 @@
|
|
"dram_de_mp", "dram_ace";
|
|
};
|
|
|
|
+ ve_clk: clk@01c2013c {
|
|
+ #clock-cells = <0>;
|
|
+ #reset-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-a10-ve-clk";
|
|
+ reg = <0x01c2013c 0x4>;
|
|
+ clocks = <&pll4>;
|
|
+ clock-output-names = "ve";
|
|
+ };
|
|
+
|
|
codec_clk: clk@01c20140 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-codec-clk";
|