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277d97e0d9
Backport few upstream changes included between v5.15 and v6.1.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
(cherry picked from commit 418aadaec9)
149 lines
4.9 KiB
Diff
149 lines
4.9 KiB
Diff
From 3c42563b30417afc8855a3b4c1b38c2f36f78657 Mon Sep 17 00:00:00 2001
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From: Sean Anderson <sean.anderson@seco.com>
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Date: Tue, 20 Sep 2022 18:12:35 -0400
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Subject: [PATCH] net: phy: aquantia: Add support for rate matching
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This adds support for rate matching for phys similar to the AQR107. We
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assume that all phys using aqr107_read_status support rate matching.
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However, it could be possible to determine support based on the firmware
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revision if there are phys discovered which do not support rate
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matching. However, as rate matching is advertised in the datasheets for
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these phys, I suspect it is supported most boards.
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Despite the name, the "config" registers are updated with the current
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rate matching method (if any). Because they appear to be updated
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automatically, I don't know if these registers can be used to disable
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rate matching.
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Signed-off-by: Sean Anderson <sean.anderson@seco.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/aquantia_main.c | 51 ++++++++++++++++++++++++++++++---
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1 file changed, 47 insertions(+), 4 deletions(-)
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--- a/drivers/net/phy/aquantia_main.c
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+++ b/drivers/net/phy/aquantia_main.c
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@@ -97,6 +97,19 @@
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#define VEND1_GLOBAL_GEN_STAT2 0xc831
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#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
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+/* The following registers all have similar layouts; first the registers... */
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+#define VEND1_GLOBAL_CFG_10M 0x0310
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+#define VEND1_GLOBAL_CFG_100M 0x031b
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+#define VEND1_GLOBAL_CFG_1G 0x031c
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+#define VEND1_GLOBAL_CFG_2_5G 0x031d
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+#define VEND1_GLOBAL_CFG_5G 0x031e
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+#define VEND1_GLOBAL_CFG_10G 0x031f
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+/* ...and now the fields */
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
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+
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#define VEND1_GLOBAL_RSVD_STAT1 0xc885
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#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
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#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
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@@ -347,40 +360,57 @@ static int aqr_read_status(struct phy_de
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static int aqr107_read_rate(struct phy_device *phydev)
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{
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+ u32 config_reg;
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
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if (val < 0)
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return val;
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+ if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
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+ phydev->duplex = DUPLEX_FULL;
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+ else
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+ phydev->duplex = DUPLEX_HALF;
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+
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switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
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case MDIO_AN_TX_VEND_STATUS1_10BASET:
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phydev->speed = SPEED_10;
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+ config_reg = VEND1_GLOBAL_CFG_10M;
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break;
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case MDIO_AN_TX_VEND_STATUS1_100BASETX:
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phydev->speed = SPEED_100;
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+ config_reg = VEND1_GLOBAL_CFG_100M;
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break;
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case MDIO_AN_TX_VEND_STATUS1_1000BASET:
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phydev->speed = SPEED_1000;
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+ config_reg = VEND1_GLOBAL_CFG_1G;
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break;
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case MDIO_AN_TX_VEND_STATUS1_2500BASET:
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phydev->speed = SPEED_2500;
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+ config_reg = VEND1_GLOBAL_CFG_2_5G;
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break;
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case MDIO_AN_TX_VEND_STATUS1_5000BASET:
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phydev->speed = SPEED_5000;
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+ config_reg = VEND1_GLOBAL_CFG_5G;
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break;
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case MDIO_AN_TX_VEND_STATUS1_10GBASET:
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phydev->speed = SPEED_10000;
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+ config_reg = VEND1_GLOBAL_CFG_10G;
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break;
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default:
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phydev->speed = SPEED_UNKNOWN;
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- break;
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+ return 0;
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}
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- if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
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- phydev->duplex = DUPLEX_FULL;
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+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
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+ if (val < 0)
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+ return val;
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+
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+ if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
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+ VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
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+ phydev->rate_matching = RATE_MATCH_PAUSE;
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else
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- phydev->duplex = DUPLEX_HALF;
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+ phydev->rate_matching = RATE_MATCH_NONE;
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return 0;
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}
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@@ -647,6 +677,16 @@ static int aqr107_wait_processor_intensi
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return 0;
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}
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+static int aqr107_get_rate_matching(struct phy_device *phydev,
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+ phy_interface_t iface)
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+{
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+ if (iface == PHY_INTERFACE_MODE_10GBASER ||
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+ iface == PHY_INTERFACE_MODE_2500BASEX ||
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+ iface == PHY_INTERFACE_MODE_NA)
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+ return RATE_MATCH_PAUSE;
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+ return RATE_MATCH_NONE;
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+}
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+
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static int aqr107_suspend(struct phy_device *phydev)
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{
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int err;
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@@ -720,6 +760,7 @@ static struct phy_driver aqr_driver[] =
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PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
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.name = "Aquantia AQR107",
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.probe = aqr107_probe,
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+ .get_rate_matching = aqr107_get_rate_matching,
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.config_init = aqr107_config_init,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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@@ -738,6 +779,7 @@ static struct phy_driver aqr_driver[] =
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PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
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.name = "Aquantia AQCS109",
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.probe = aqr107_probe,
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+ .get_rate_matching = aqr107_get_rate_matching,
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.config_init = aqcs109_config_init,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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@@ -764,6 +806,7 @@ static struct phy_driver aqr_driver[] =
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PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
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.name = "Aquantia AQR113C",
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.probe = aqr107_probe,
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+ .get_rate_matching = aqr107_get_rate_matching,
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.config_init = aqr107_config_init,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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