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6734cbd9f7
No manual changes needed.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 0307571124)
85 lines
3.5 KiB
Diff
85 lines
3.5 KiB
Diff
From 194ec04b3a9e7fa97d1fbef296410631bc3cf1c8 Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Sun, 20 Mar 2022 18:00:00 +0800
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Subject: [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,
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4}GQ5xExxG
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Add support for:
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GD5F2GQ5{U,R}ExxG
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GD5F4GQ6{U,R}ExxG
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These chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io.
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Besides that and memory layout, they are identical to their 1G variant.
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-5-gch981213@gmail.com
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---
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drivers/mtd/nand/spi/gigadevice.c | 48 +++++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -47,6 +47,14 @@ static SPINAND_OP_VARIANTS(read_cache_va
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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@@ -393,6 +401,46 @@ static const struct spinand_info gigadev
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GQ5UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GQ5RExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ6UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ6RExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq5xexxg_ecc_get_status)),
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};
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