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2f4bb69664
CI is supposed to catch all of these. Some of these predate CI. Signed-off-by: Rosen Penev <rosenp@gmail.com>
95 lines
3.1 KiB
Diff
95 lines
3.1 KiB
Diff
From 725595e667cc4423347c255da8ca4c5b3aa0980a Mon Sep 17 00:00:00 2001
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From: Vincent Chen <vincent.chen@sifive.com>
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Date: Mon, 15 Nov 2021 03:31:04 -0800
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Subject: [PATCH 2/8] board: sifive: spl: Initialized the PWM setting in the
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SPL stage
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LEDs and multiple fans can be controlled by SPL. This patch ensures
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that all fans have been enabled in the SPL stage. In addition, the
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LED's color will be set to yellow.
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---
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board/sifive/unmatched/Makefile | 1 +
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board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++
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board/sifive/unmatched/spl.c | 2 ++
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3 files changed, 60 insertions(+)
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create mode 100644 board/sifive/unmatched/pwm.c
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--- a/board/sifive/unmatched/Makefile
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+++ b/board/sifive/unmatched/Makefile
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@@ -9,3 +9,4 @@ obj-y += spl.o
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else
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obj-y += unmatched.o
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endif
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+obj-y += pwm.o
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--- /dev/null
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+++ b/board/sifive/unmatched/pwm.c
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@@ -0,0 +1,57 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (c) 2021, SiFive Inc
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+ *
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+ * Authors:
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+ * Vincent Chen <vincent.chen@sifive.com>
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+ * David Abdurachmanov <david.abdurachmanov@sifive.com>
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+ */
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+
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+#include <linux/io.h>
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+#include <asm/arch/eeprom.h>
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+
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+struct pwm_sifive_regs {
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+ unsigned int cfg; /* PWM configuration register */
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+ unsigned int pad0; /* Reserved */
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+ unsigned int cnt; /* PWM count register */
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+ unsigned int pad1; /* Reserved */
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+ unsigned int pwms; /* Scaled PWM count register */
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+ unsigned int pad2; /* Reserved */
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+ unsigned int pad3; /* Reserved */
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+ unsigned int pad4; /* Reserved */
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+ unsigned int cmp0; /* PWM 0 compare register */
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+ unsigned int cmp1; /* PWM 1 compare register */
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+ unsigned int cmp2; /* PWM 2 compare register */
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+ unsigned int cmp3; /* PWM 3 compare register */
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+};
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+
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+#define PWM0_BASE 0x10020000
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+#define PWM1_BASE 0x10021000
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+#define PWM_CFG_INIT 0x1000
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+#define PWM_CMP_ENABLE_VAL 0x0
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+#define PWM_CMP_DISABLE_VAL 0xffff
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+
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+void pwm_device_init(void)
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+{
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+ struct pwm_sifive_regs *pwm0, *pwm1;
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+ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
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+ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
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+ /* Set the 3-color PWM LEDs to yellow in SPL */
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
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+ writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
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+
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
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+ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
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+ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
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+ so here sets the initial value of PWM_COMP0 as DISABLE */
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+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
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+ else
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
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+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
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+}
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--- a/board/sifive/unmatched/spl.c
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+++ b/board/sifive/unmatched/spl.c
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@@ -90,6 +90,8 @@ int spl_board_init_f(void)
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goto end;
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}
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+ pwm_device_init();
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+
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ret = spl_gemgxl_init();
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if (ret) {
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debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
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