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https://github.com/openwrt/openwrt.git
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d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
2139 lines
50 KiB
Diff
2139 lines
50 KiB
Diff
From ce792f7abd4294ebba76f76d9d7aa90c7970de8e Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Thu, 4 Aug 2022 23:35:09 -0500
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Subject: [PATCH 78/90] riscv: Add Allwinner D1 devicetrees
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/riscv/dts/Makefile | 9 +
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.../riscv/dts/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
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.../dts/sun20i-d1-common-regulators.dtsi | 51 +
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arch/riscv/dts/sun20i-d1-devterm-v3.14.dts | 37 +
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.../dts/sun20i-d1-dongshan-nezha-stu.dts | 114 +++
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.../dts/sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
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.../dts/sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
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.../dts/sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
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arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts | 74 ++
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arch/riscv/dts/sun20i-d1-lichee-rv.dts | 84 ++
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arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts | 128 +++
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arch/riscv/dts/sun20i-d1-nezha.dts | 171 ++++
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arch/riscv/dts/sun20i-d1.dtsi | 900 ++++++++++++++++++
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arch/riscv/dts/sunxi-u-boot.dtsi | 68 ++
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include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 +
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include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 +
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16 files changed, 2044 insertions(+)
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create mode 100644 arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-common-regulators.dtsi
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create mode 100644 arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
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create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
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create mode 100644 arch/riscv/dts/sun20i-d1-nezha.dts
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create mode 100644 arch/riscv/dts/sun20i-d1.dtsi
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create mode 100644 arch/riscv/dts/sunxi-u-boot.dtsi
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create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h
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create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h
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--- a/arch/riscv/dts/Makefile
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+++ b/arch/riscv/dts/Makefile
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@@ -7,6 +7,15 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) +
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dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
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dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
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dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-clockworkpi-v3.14.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-devterm-v3.14.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-dongshan-nezha-stu.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-480p.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-720p.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-dock.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-mangopi-mq-pro.dtb
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+dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-nezha.dtb
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include $(srctree)/scripts/Makefile.dts
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--- /dev/null
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+++ b/arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
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@@ -0,0 +1,242 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+#include "sun20i-d1.dtsi"
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+#include "sun20i-d1-common-regulators.dtsi"
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+
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+/ {
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+ model = "ClockworkPi v3.14 (R-01)";
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+ compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
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+
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+ aliases {
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+ ethernet0 = &ap6256;
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+ mmc0 = &mmc0;
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ /*
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+ * This regulator is PWM-controlled, but the PWM controller is not
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+ * yet supported, so fix the regulator to its default voltage.
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+ */
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+ reg_vdd_cpu: vdd-cpu {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd-cpu";
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1100000>;
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+ vin-supply = <®_vcc>;
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+ };
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+
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+ wifi_pwrseq: wifi-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
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+ };
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+};
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+
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+&cpu0 {
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+ cpu-supply = <®_vdd_cpu>;
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+};
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+
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+&ehci1 {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ pinctrl-0 = <&i2c0_pb10_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ axp221: pmic@34 {
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+ compatible = "x-powers,axp228", "x-powers,axp221";
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+ reg = <0x34>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ ac_power_supply: ac-power {
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+ compatible = "x-powers,axp221-ac-power-supply";
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+ };
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+
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+ axp_adc: adc {
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+ compatible = "x-powers,axp221-adc";
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+ #io-channel-cells = <1>;
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+ };
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+
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+ battery_power_supply: battery-power {
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+ compatible = "x-powers,axp221-battery-power-supply";
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+ };
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+
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+ regulators {
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+ x-powers,dcdc-freq = <3000>;
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+
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+ reg_dcdc1: dcdc1 {
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+ regulator-name = "sys-3v3";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_dcdc3: dcdc3 {
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+ regulator-name = "sys-1v8";
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ };
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+
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+ reg_aldo1: aldo1 {
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+ regulator-name = "aud-3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_aldo2: aldo2 {
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+ regulator-name = "disp-3v3";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_aldo3: aldo3 {
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+ regulator-name = "vdd-wifi";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ };
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+
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+ /* DLDO1 and ELDO1-3 are connected in parallel. */
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+ reg_dldo1: dldo1 {
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+ regulator-name = "vbat-wifi-a";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ /* DLDO2-DLDO4 are connected in parallel. */
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+ reg_dldo2: dldo2 {
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+ regulator-name = "vcc-3v3-ext-a";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_dldo3: dldo3 {
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+ regulator-name = "vcc-3v3-ext-b";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_dldo4: dldo4 {
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+ regulator-name = "vcc-3v3-ext-c";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_eldo1: eldo1 {
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+ regulator-name = "vbat-wifi-b";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_eldo2: eldo2 {
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+ regulator-name = "vbat-wifi-c";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_eldo3: eldo3 {
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+ regulator-name = "vbat-wifi-d";
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+ };
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+
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+ usb_power_supply: usb-power {
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+ compatible = "x-powers,axp221-usb-power-supply";
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+ status = "disabled";
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+ };
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+ };
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+};
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+
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+&mmc0 {
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+ broken-cd;
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+ bus-width = <4>;
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+ disable-wp;
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+ vmmc-supply = <®_dcdc1>;
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+ vqmmc-supply = <®_vcc_3v3>;
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+ pinctrl-0 = <&mmc0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&mmc1 {
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+ bus-width = <4>;
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+ mmc-pwrseq = <&wifi_pwrseq>;
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+ non-removable;
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+ vmmc-supply = <®_dldo1>;
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+ vqmmc-supply = <®_aldo3>;
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+ pinctrl-0 = <&mmc1_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ ap6256: wifi@1 {
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+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
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+ reg = <1>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
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+ interrupt-names = "host-wake";
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+ };
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+};
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+
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+&ohci1 {
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+ status = "okay";
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+};
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+
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+&pio {
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+ vcc-pg-supply = <®_ldoa>;
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+};
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+
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+&uart0 {
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+ pinctrl-0 = <&uart0_pb8_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ uart-has-rtscts;
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+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ bluetooth {
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+ compatible = "brcm,bcm4345c5";
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+ interrupt-parent = <&pio>;
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+ interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
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+ device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
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+ shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
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+ max-speed = <1500000>;
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+ vbat-supply = <®_dldo1>;
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+ vddio-supply = <®_aldo3>;
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+ };
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+};
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+
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+&usb_otg {
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&usbphy {
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+ usb0_vbus_power-supply = <&ac_power_supply>;
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+ status = "okay";
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+};
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--- /dev/null
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+++ b/arch/riscv/dts/sun20i-d1-common-regulators.dtsi
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@@ -0,0 +1,51 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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+
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+/ {
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+ reg_vcc: vcc {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ reg_vcc_3v3: vcc-3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <®_vcc>;
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+ };
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+};
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+
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+&lradc {
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+ vref-supply = <®_aldo>;
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+};
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+
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+&pio {
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+ vcc-pb-supply = <®_vcc_3v3>;
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+ vcc-pc-supply = <®_vcc_3v3>;
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+ vcc-pd-supply = <®_vcc_3v3>;
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+ vcc-pe-supply = <®_vcc_3v3>;
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+ vcc-pf-supply = <®_vcc_3v3>;
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+ vcc-pg-supply = <®_vcc_3v3>;
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+};
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+
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+®_aldo {
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ vdd33-supply = <®_vcc_3v3>;
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+};
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+
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+®_hpldo {
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ hpldoin-supply = <®_vcc_3v3>;
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+};
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+
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+®_ldoa {
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ ldo-in-supply = <®_vcc_3v3>;
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+};
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--- /dev/null
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+++ b/arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
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@@ -0,0 +1,37 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
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+
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+/dts-v1/;
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+
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+#include "sun20i-d1-clockworkpi-v3.14.dts"
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+
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+/ {
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+ model = "Clockwork DevTerm (R-01)";
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+ compatible = "clockwork,r-01-devterm-v3.14",
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+ "clockwork,r-01-clockworkpi-v3.14",
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+ "allwinner,sun20i-d1";
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+
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+ fan {
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+ compatible = "gpio-fan";
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+ gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
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+ gpio-fan,speed-map = <0 0>,
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+ <6000 1>;
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+ #cooling-cells = <2>;
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+ };
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+
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+ i2c-gpio-0 {
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+ compatible = "i2c-gpio";
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+ sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
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+ scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ adc@54 {
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+ compatible = "ti,adc101c";
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+ reg = <0x54>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
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+ vref-supply = <®_dldo2>;
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
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@@ -0,0 +1,114 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/leds/common.h>
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+
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+#include "sun20i-d1.dtsi"
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+#include "sun20i-d1-common-regulators.dtsi"
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+
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+/ {
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+ model = "Dongshan Nezha STU";
|
|
+ compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = &emac;
|
|
+ mmc0 = &mmc0;
|
|
+ serial0 = &uart0;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ compatible = "gpio-leds";
|
|
+
|
|
+ led-0 {
|
|
+ color = <LED_COLOR_ID_GREEN>;
|
|
+ function = LED_FUNCTION_STATUS;
|
|
+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reg_usbvbus: usbvbus {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "usbvbus";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
|
|
+ enable-active-high;
|
|
+ vin-supply = <®_vcc>;
|
|
+ };
|
|
+
|
|
+ /*
|
|
+ * This regulator is PWM-controlled, but the PWM controller is not
|
|
+ * yet supported, so fix the regulator to its default voltage.
|
|
+ */
|
|
+ reg_vdd_cpu: vdd-cpu {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vdd-cpu";
|
|
+ regulator-min-microvolt = <1100000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ vin-supply = <®_vcc>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ cpu-supply = <®_vdd_cpu>;
|
|
+};
|
|
+
|
|
+&ehci0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&emac {
|
|
+ pinctrl-0 = <&rgmii_pe_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ phy-handle = <&ext_rgmii_phy>;
|
|
+ phy-mode = "rgmii-id";
|
|
+ phy-supply = <®_vcc_3v3>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mdio {
|
|
+ ext_rgmii_phy: ethernet-phy@1 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ broken-cd;
|
|
+ bus-width = <4>;
|
|
+ disable-wp;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ohci0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-0 = <&uart0_pb8_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_otg {
|
|
+ dr_mode = "otg";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
|
|
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
|
|
+ usb0_vbus-supply = <®_usbvbus>;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
|
|
@@ -0,0 +1,29 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Sipeed Lichee RV 86 Panel (480p)";
|
|
+ compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
|
|
+ "allwinner,sun20i-d1";
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ pinctrl-0 = <&i2c2_pb0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ touchscreen@48 {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x48>;
|
|
+ interrupt-parent = <&pio>;
|
|
+ interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
|
|
+ iovcc-supply = <®_vcc_3v3>;
|
|
+ reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <480>;
|
|
+ vcc-supply = <®_vcc_3v3>;
|
|
+ wakeup-source;
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
|
|
@@ -0,0 +1,10 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Sipeed Lichee RV 86 Panel (720p)";
|
|
+ compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
|
|
+ "allwinner,sun20i-d1";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
|
|
@@ -0,0 +1,92 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+#include "sun20i-d1-lichee-rv.dts"
|
|
+
|
|
+/ {
|
|
+ aliases {
|
|
+ ethernet0 = &emac;
|
|
+ ethernet1 = &xr829;
|
|
+ };
|
|
+
|
|
+ /* PC1 is repurposed as BT_WAKE_AP */
|
|
+ /delete-node/ leds;
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ clocks = <&ccu CLK_FANOUT1>;
|
|
+ clock-names = "ext_clock";
|
|
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
|
|
+ assigned-clocks = <&ccu CLK_FANOUT1>;
|
|
+ assigned-clock-rates = <32768>;
|
|
+ pinctrl-0 = <&clk_pg11_pin>;
|
|
+ pinctrl-names = "default";
|
|
+ };
|
|
+};
|
|
+
|
|
+&ehci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&emac {
|
|
+ pinctrl-0 = <&rmii_pe_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ phy-handle = <&ext_rmii_phy>;
|
|
+ phy-mode = "rmii";
|
|
+ phy-supply = <®_vcc_3v3>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mdio {
|
|
+ ext_rmii_phy: ethernet-phy@1 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <1>;
|
|
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
|
|
+ };
|
|
+};
|
|
+
|
|
+&mmc1 {
|
|
+ bus-width = <4>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ non-removable;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc1_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ xr829: wifi@1 {
|
|
+ reg = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&ohci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pio {
|
|
+ clk_pg11_pin: clk-pg11-pin {
|
|
+ pins = "PG11";
|
|
+ function = "clk";
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ uart-has-rtscts;
|
|
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ /* XR829 bluetooth is connected here */
|
|
+};
|
|
+
|
|
+&usb_otg {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ /* PD20 and PD21 are repurposed for the LCD panel */
|
|
+ /delete-property/ usb0_id_det-gpios;
|
|
+ /delete-property/ usb0_vbus_det-gpios;
|
|
+ usb1_vbus-supply = <®_vcc>;
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
|
|
@@ -0,0 +1,74 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
|
|
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+#include <dt-bindings/input/input.h>
|
|
+
|
|
+#include "sun20i-d1-lichee-rv.dts"
|
|
+
|
|
+/ {
|
|
+ model = "Sipeed Lichee RV Dock";
|
|
+ compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
|
|
+ "allwinner,sun20i-d1";
|
|
+
|
|
+ aliases {
|
|
+ ethernet1 = &rtl8723ds;
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
|
|
+ };
|
|
+};
|
|
+
|
|
+&ehci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&lradc {
|
|
+ status = "okay";
|
|
+
|
|
+ button-220 {
|
|
+ label = "OK";
|
|
+ linux,code = <KEY_OK>;
|
|
+ channel = <0>;
|
|
+ voltage = <220000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&mmc1 {
|
|
+ bus-width = <4>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ non-removable;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc1_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ rtl8723ds: wifi@1 {
|
|
+ reg = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&ohci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ uart-has-rtscts;
|
|
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ bluetooth {
|
|
+ compatible = "realtek,rtl8723ds-bt";
|
|
+ device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
|
|
+ enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
|
|
+ host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
|
|
+ };
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ usb1_vbus-supply = <®_vcc>;
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1-lichee-rv.dts
|
|
@@ -0,0 +1,84 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
|
|
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/leds/common.h>
|
|
+
|
|
+#include "sun20i-d1.dtsi"
|
|
+#include "sun20i-d1-common-regulators.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Sipeed Lichee RV";
|
|
+ compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
|
|
+
|
|
+ aliases {
|
|
+ mmc0 = &mmc0;
|
|
+ serial0 = &uart0;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ compatible = "gpio-leds";
|
|
+
|
|
+ led-0 {
|
|
+ color = <LED_COLOR_ID_GREEN>;
|
|
+ function = LED_FUNCTION_STATUS;
|
|
+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reg_vdd_cpu: vdd-cpu {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vdd-cpu";
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ vin-supply = <®_vcc>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ cpu-supply = <®_vdd_cpu>;
|
|
+};
|
|
+
|
|
+&ehci0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ broken-cd;
|
|
+ bus-width = <4>;
|
|
+ disable-wp;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ohci0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-0 = <&uart0_pb8_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_otg {
|
|
+ dr_mode = "otg";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
|
|
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
|
|
+ usb0_vbus-supply = <®_vcc>;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
|
|
@@ -0,0 +1,128 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+#include "sun20i-d1.dtsi"
|
|
+#include "sun20i-d1-common-regulators.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "MangoPi MQ Pro";
|
|
+ compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = &rtl8723ds;
|
|
+ mmc0 = &mmc0;
|
|
+ serial0 = &uart0;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reg_avdd2v8: avdd2v8 {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "avdd2v8";
|
|
+ regulator-min-microvolt = <2800000>;
|
|
+ regulator-max-microvolt = <2800000>;
|
|
+ vin-supply = <®_vcc_3v3>;
|
|
+ };
|
|
+
|
|
+ reg_dvdd: dvdd {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "dvdd";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ vin-supply = <®_vcc_3v3>;
|
|
+ };
|
|
+
|
|
+ reg_vdd_cpu: vdd-cpu {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vdd-cpu";
|
|
+ regulator-min-microvolt = <1100000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ vin-supply = <®_vcc>;
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ cpu-supply = <®_vdd_cpu>;
|
|
+};
|
|
+
|
|
+&ehci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ bus-width = <4>;
|
|
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
|
|
+ disable-wp;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mmc1 {
|
|
+ bus-width = <4>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ non-removable;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc1_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ rtl8723ds: wifi@1 {
|
|
+ reg = <1>;
|
|
+ interrupt-parent = <&pio>;
|
|
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
|
|
+ interrupt-names = "host-wake";
|
|
+ };
|
|
+};
|
|
+
|
|
+&ohci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pio {
|
|
+ vcc-pe-supply = <®_avdd2v8>;
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-0 = <&uart0_pb8_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ uart-has-rtscts;
|
|
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ bluetooth {
|
|
+ compatible = "realtek,rtl8723ds-bt";
|
|
+ device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
|
|
+ enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
|
|
+ host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
|
|
+ };
|
|
+};
|
|
+
|
|
+&usb_otg {
|
|
+ dr_mode = "peripheral";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ usb0_vbus-supply = <®_vcc>;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1-nezha.dts
|
|
@@ -0,0 +1,171 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/input/input.h>
|
|
+
|
|
+#include "sun20i-d1.dtsi"
|
|
+#include "sun20i-d1-common-regulators.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Allwinner D1 Nezha";
|
|
+ compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = &emac;
|
|
+ ethernet1 = &xr829;
|
|
+ mmc0 = &mmc0;
|
|
+ serial0 = &uart0;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reg_usbvbus: usbvbus {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "usbvbus";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
|
|
+ enable-active-high;
|
|
+ vin-supply = <®_vcc>;
|
|
+ };
|
|
+
|
|
+ /*
|
|
+ * This regulator is PWM-controlled, but the PWM controller is not
|
|
+ * yet supported, so fix the regulator to its default voltage.
|
|
+ */
|
|
+ reg_vdd_cpu: vdd-cpu {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vdd-cpu";
|
|
+ regulator-min-microvolt = <1100000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ vin-supply = <®_vcc>;
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ cpu-supply = <®_vdd_cpu>;
|
|
+};
|
|
+
|
|
+&ehci0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ehci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&emac {
|
|
+ pinctrl-0 = <&rgmii_pe_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ phy-handle = <&ext_rgmii_phy>;
|
|
+ phy-mode = "rgmii-id";
|
|
+ phy-supply = <®_vcc_3v3>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ pinctrl-0 = <&i2c2_pb0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ pcf8574a: gpio@38 {
|
|
+ compatible = "nxp,pcf8574a";
|
|
+ reg = <0x38>;
|
|
+ interrupt-parent = <&pio>;
|
|
+ interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
|
|
+ interrupt-controller;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&lradc {
|
|
+ status = "okay";
|
|
+
|
|
+ button-160 {
|
|
+ label = "OK";
|
|
+ linux,code = <KEY_OK>;
|
|
+ channel = <0>;
|
|
+ voltage = <160000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&mdio {
|
|
+ ext_rgmii_phy: ethernet-phy@1 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ bus-width = <4>;
|
|
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
|
|
+ disable-wp;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mmc1 {
|
|
+ bus-width = <4>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ non-removable;
|
|
+ vmmc-supply = <®_vcc_3v3>;
|
|
+ vqmmc-supply = <®_vcc_3v3>;
|
|
+ pinctrl-0 = <&mmc1_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ xr829: wifi@1 {
|
|
+ reg = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&ohci0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ohci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-0 = <&uart0_pb8_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ uart-has-rtscts;
|
|
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ /* XR829 bluetooth is connected here */
|
|
+};
|
|
+
|
|
+&usb_otg {
|
|
+ dr_mode = "otg";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
|
|
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
|
|
+ usb0_vbus-supply = <®_usbvbus>;
|
|
+ usb1_vbus-supply = <®_vcc>;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sun20i-d1.dtsi
|
|
@@ -0,0 +1,900 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
|
|
+
|
|
+#include <dt-bindings/clock/sun6i-rtc.h>
|
|
+#include <dt-bindings/clock/sun8i-de2.h>
|
|
+#include <dt-bindings/clock/sun8i-tcon-top.h>
|
|
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
|
|
+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
|
|
+#include <dt-bindings/interrupt-controller/irq.h>
|
|
+#include <dt-bindings/reset/sun8i-de2.h>
|
|
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
|
|
+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
+
|
|
+/ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ cpus {
|
|
+ timebase-frequency = <24000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cpu0: cpu@0 {
|
|
+ compatible = "thead,c906", "riscv";
|
|
+ device_type = "cpu";
|
|
+ reg = <0>;
|
|
+ clocks = <&ccu CLK_RISCV>;
|
|
+ clock-frequency = <24000000>;
|
|
+ d-cache-block-size = <64>;
|
|
+ d-cache-sets = <256>;
|
|
+ d-cache-size = <32768>;
|
|
+ i-cache-block-size = <64>;
|
|
+ i-cache-sets = <128>;
|
|
+ i-cache-size = <32768>;
|
|
+ mmu-type = "riscv,sv39";
|
|
+ riscv,isa = "rv64imafdc";
|
|
+ #cooling-cells = <2>;
|
|
+
|
|
+ cpu0_intc: interrupt-controller {
|
|
+ compatible = "riscv,cpu-intc";
|
|
+ interrupt-controller;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ de: display-engine {
|
|
+ compatible = "allwinner,sun20i-d1-display-engine";
|
|
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ osc24M: osc24M-clk {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ clock-output-names = "osc24M";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ compatible = "simple-bus";
|
|
+ ranges;
|
|
+ interrupt-parent = <&plic>;
|
|
+ dma-noncoherent;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ dsp_wdt: watchdog@1700400 {
|
|
+ compatible = "allwinner,sun20i-d1-wdt";
|
|
+ reg = <0x1700400 0x20>;
|
|
+ interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
|
|
+ clock-names = "hosc", "losc";
|
|
+ status = "reserved";
|
|
+ };
|
|
+
|
|
+ pio: pinctrl@2000000 {
|
|
+ compatible = "allwinner,sun20i-d1-pinctrl";
|
|
+ reg = <0x2000000 0x800>;
|
|
+ interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <87 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <89 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <91 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <93 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <95 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_APB0>,
|
|
+ <&osc24M>,
|
|
+ <&rtc CLK_OSC32K>;
|
|
+ clock-names = "apb", "hosc", "losc";
|
|
+ gpio-controller;
|
|
+ interrupt-controller;
|
|
+ #gpio-cells = <3>;
|
|
+ #interrupt-cells = <3>;
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ i2c0_pb10_pins: i2c0-pb10-pins {
|
|
+ pins = "PB10", "PB11";
|
|
+ function = "i2c0";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ i2c2_pb0_pins: i2c2-pb0-pins {
|
|
+ pins = "PB0", "PB1";
|
|
+ function = "i2c2";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ lcd_rgb666_pins: lcd-rgb666-pins {
|
|
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
|
|
+ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
|
|
+ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
|
|
+ "PD18", "PD19", "PD20", "PD21";
|
|
+ function = "lcd0";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ mmc0_pins: mmc0-pins {
|
|
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
|
+ function = "mmc0";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ mmc1_pins: mmc1-pins {
|
|
+ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
|
|
+ function = "mmc1";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ mmc2_pins: mmc2-pins {
|
|
+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
|
|
+ function = "mmc2";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ rgmii_pe_pins: rgmii-pe-pins {
|
|
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
|
|
+ "PE5", "PE6", "PE7", "PE8", "PE9",
|
|
+ "PE11", "PE12", "PE13", "PE14", "PE15";
|
|
+ function = "emac";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ rmii_pe_pins: rmii-pe-pins {
|
|
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
|
|
+ "PE5", "PE6", "PE7", "PE8", "PE9";
|
|
+ function = "emac";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ uart0_pb8_pins: uart0-pb8-pins {
|
|
+ pins = "PB8", "PB9";
|
|
+ function = "uart0";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ uart1_pg6_pins: uart1-pg6-pins {
|
|
+ pins = "PG6", "PG7";
|
|
+ function = "uart1";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
|
|
+ pins = "PG8", "PG9";
|
|
+ function = "uart1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ccu: clock-controller@2001000 {
|
|
+ compatible = "allwinner,sun20i-d1-ccu";
|
|
+ reg = <0x2001000 0x1000>;
|
|
+ clocks = <&osc24M>,
|
|
+ <&rtc CLK_OSC32K>,
|
|
+ <&rtc CLK_IOSC>;
|
|
+ clock-names = "hosc", "losc", "iosc";
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ lradc: keys@2009800 {
|
|
+ compatible = "allwinner,sun20i-d1-lradc",
|
|
+ "allwinner,sun50i-r329-lradc";
|
|
+ reg = <0x2009800 0x400>;
|
|
+ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_LRADC>;
|
|
+ resets = <&ccu RST_BUS_LRADC>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ codec: audio-codec@2030000 {
|
|
+ compatible = "simple-mfd", "syscon";
|
|
+ reg = <0x2030000 0x1000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ regulators@2030348 {
|
|
+ compatible = "allwinner,sun20i-d1-analog-ldos";
|
|
+ reg = <0x2030348 0x4>;
|
|
+ nvmem-cells = <&bg_trim>;
|
|
+ nvmem-cell-names = "bg_trim";
|
|
+
|
|
+ reg_aldo: aldo {
|
|
+ };
|
|
+
|
|
+ reg_hpldo: hpldo {
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2s0: i2s@2032000 {
|
|
+ compatible = "allwinner,sun20i-d1-i2s",
|
|
+ "allwinner,sun50i-r329-i2s";
|
|
+ reg = <0x2032000 0x1000>;
|
|
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2S0>,
|
|
+ <&ccu CLK_I2S0>;
|
|
+ clock-names = "apb", "mod";
|
|
+ resets = <&ccu RST_BUS_I2S0>;
|
|
+ dmas = <&dma 3>, <&dma 3>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ #sound-dai-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2s1: i2s@2033000 {
|
|
+ compatible = "allwinner,sun20i-d1-i2s",
|
|
+ "allwinner,sun50i-r329-i2s";
|
|
+ reg = <0x2033000 0x1000>;
|
|
+ interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2S1>,
|
|
+ <&ccu CLK_I2S1>;
|
|
+ clock-names = "apb", "mod";
|
|
+ resets = <&ccu RST_BUS_I2S1>;
|
|
+ dmas = <&dma 4>, <&dma 4>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ #sound-dai-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2s2: i2s@2034000 {
|
|
+ compatible = "allwinner,sun20i-d1-i2s",
|
|
+ "allwinner,sun50i-r329-i2s";
|
|
+ reg = <0x2034000 0x1000>;
|
|
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2S2>,
|
|
+ <&ccu CLK_I2S2>;
|
|
+ clock-names = "apb", "mod";
|
|
+ resets = <&ccu RST_BUS_I2S2>;
|
|
+ dmas = <&dma 5>, <&dma 5>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ #sound-dai-cells = <0>;
|
|
+ };
|
|
+
|
|
+ timer: timer@2050000 {
|
|
+ compatible = "allwinner,sun20i-d1-timer",
|
|
+ "allwinner,sun8i-a23-timer";
|
|
+ reg = <0x2050000 0xa0>;
|
|
+ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <76 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&osc24M>;
|
|
+ };
|
|
+
|
|
+ wdt: watchdog@20500a0 {
|
|
+ compatible = "allwinner,sun20i-d1-wdt-reset",
|
|
+ "allwinner,sun20i-d1-wdt";
|
|
+ reg = <0x20500a0 0x20>;
|
|
+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
|
|
+ clock-names = "hosc", "losc";
|
|
+ status = "reserved";
|
|
+ };
|
|
+
|
|
+ uart0: serial@2500000 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x2500000 0x400>;
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_UART0>;
|
|
+ resets = <&ccu RST_BUS_UART0>;
|
|
+ dmas = <&dma 14>, <&dma 14>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart1: serial@2500400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x2500400 0x400>;
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_UART1>;
|
|
+ resets = <&ccu RST_BUS_UART1>;
|
|
+ dmas = <&dma 15>, <&dma 15>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart2: serial@2500800 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x2500800 0x400>;
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_UART2>;
|
|
+ resets = <&ccu RST_BUS_UART2>;
|
|
+ dmas = <&dma 16>, <&dma 16>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@2500c00 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x2500c00 0x400>;
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_UART3>;
|
|
+ resets = <&ccu RST_BUS_UART3>;
|
|
+ dmas = <&dma 17>, <&dma 17>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart4: serial@2501000 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x2501000 0x400>;
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_UART4>;
|
|
+ resets = <&ccu RST_BUS_UART4>;
|
|
+ dmas = <&dma 18>, <&dma 18>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart5: serial@2501400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x2501400 0x400>;
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_UART5>;
|
|
+ resets = <&ccu RST_BUS_UART5>;
|
|
+ dmas = <&dma 19>, <&dma 19>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@2502000 {
|
|
+ compatible = "allwinner,sun20i-d1-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x2502000 0x400>;
|
|
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C0>;
|
|
+ resets = <&ccu RST_BUS_I2C0>;
|
|
+ dmas = <&dma 43>, <&dma 43>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@2502400 {
|
|
+ compatible = "allwinner,sun20i-d1-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x2502400 0x400>;
|
|
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C1>;
|
|
+ resets = <&ccu RST_BUS_I2C1>;
|
|
+ dmas = <&dma 44>, <&dma 44>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@2502800 {
|
|
+ compatible = "allwinner,sun20i-d1-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x2502800 0x400>;
|
|
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C2>;
|
|
+ resets = <&ccu RST_BUS_I2C2>;
|
|
+ dmas = <&dma 45>, <&dma 45>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@2502c00 {
|
|
+ compatible = "allwinner,sun20i-d1-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x2502c00 0x400>;
|
|
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C3>;
|
|
+ resets = <&ccu RST_BUS_I2C3>;
|
|
+ dmas = <&dma 46>, <&dma 46>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ syscon: syscon@3000000 {
|
|
+ compatible = "allwinner,sun20i-d1-system-control";
|
|
+ reg = <0x3000000 0x1000>;
|
|
+ ranges;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ regulators@3000150 {
|
|
+ compatible = "allwinner,sun20i-d1-system-ldos";
|
|
+ reg = <0x3000150 0x4>;
|
|
+
|
|
+ reg_ldoa: ldoa {
|
|
+ };
|
|
+
|
|
+ reg_ldob: ldob {
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dma: dma-controller@3002000 {
|
|
+ compatible = "allwinner,sun20i-d1-dma";
|
|
+ reg = <0x3002000 0x1000>;
|
|
+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
|
|
+ clock-names = "bus", "mbus";
|
|
+ resets = <&ccu RST_BUS_DMA>;
|
|
+ dma-channels = <16>;
|
|
+ dma-requests = <48>;
|
|
+ #dma-cells = <1>;
|
|
+ };
|
|
+
|
|
+ sid: efuse@3006000 {
|
|
+ compatible = "allwinner,sun20i-d1-sid";
|
|
+ reg = <0x3006000 0x1000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ ths_calib: ths-calib@14 {
|
|
+ reg = <0x14 0x4>;
|
|
+ };
|
|
+
|
|
+ bg_trim: bg-trim@28 {
|
|
+ reg = <0x28 0x4>;
|
|
+ bits = <16 8>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mbus: dram-controller@3102000 {
|
|
+ compatible = "allwinner,sun20i-d1-mbus";
|
|
+ reg = <0x3102000 0x1000>,
|
|
+ <0x3103000 0x1000>;
|
|
+ reg-names = "mbus", "dram";
|
|
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_MBUS>,
|
|
+ <&ccu CLK_DRAM>,
|
|
+ <&ccu CLK_BUS_DRAM>;
|
|
+ clock-names = "mbus", "dram", "bus";
|
|
+ dma-ranges = <0 0x40000000 0x80000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ #interconnect-cells = <1>;
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@4020000 {
|
|
+ compatible = "allwinner,sun20i-d1-mmc";
|
|
+ reg = <0x4020000 0x1000>;
|
|
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC0>;
|
|
+ reset-names = "ahb";
|
|
+ cap-sd-highspeed;
|
|
+ max-frequency = <150000000>;
|
|
+ no-mmc;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc1: mmc@4021000 {
|
|
+ compatible = "allwinner,sun20i-d1-mmc";
|
|
+ reg = <0x4021000 0x1000>;
|
|
+ interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC1>;
|
|
+ reset-names = "ahb";
|
|
+ cap-sd-highspeed;
|
|
+ max-frequency = <150000000>;
|
|
+ no-mmc;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc2: mmc@4022000 {
|
|
+ compatible = "allwinner,sun20i-d1-emmc",
|
|
+ "allwinner,sun50i-a100-emmc";
|
|
+ reg = <0x4022000 0x1000>;
|
|
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC2>;
|
|
+ reset-names = "ahb";
|
|
+ cap-mmc-highspeed;
|
|
+ max-frequency = <150000000>;
|
|
+ mmc-ddr-1_8v;
|
|
+ mmc-ddr-3_3v;
|
|
+ no-sd;
|
|
+ no-sdio;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ usb_otg: usb@4100000 {
|
|
+ compatible = "allwinner,sun20i-d1-musb",
|
|
+ "allwinner,sun8i-a33-musb";
|
|
+ reg = <0x4100000 0x400>;
|
|
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "mc";
|
|
+ clocks = <&ccu CLK_BUS_OTG>;
|
|
+ resets = <&ccu RST_BUS_OTG>;
|
|
+ extcon = <&usbphy 0>;
|
|
+ phys = <&usbphy 0>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usbphy: phy@4100400 {
|
|
+ compatible = "allwinner,sun20i-d1-usb-phy";
|
|
+ reg = <0x4100400 0x100>,
|
|
+ <0x4101800 0x100>,
|
|
+ <0x4200800 0x100>;
|
|
+ reg-names = "phy_ctrl",
|
|
+ "pmu0",
|
|
+ "pmu1";
|
|
+ clocks = <&osc24M>,
|
|
+ <&osc24M>;
|
|
+ clock-names = "usb0_phy",
|
|
+ "usb1_phy";
|
|
+ resets = <&ccu RST_USB_PHY0>,
|
|
+ <&ccu RST_USB_PHY1>;
|
|
+ reset-names = "usb0_reset",
|
|
+ "usb1_reset";
|
|
+ status = "disabled";
|
|
+ #phy-cells = <1>;
|
|
+ };
|
|
+
|
|
+ ehci0: usb@4101000 {
|
|
+ compatible = "allwinner,sun20i-d1-ehci",
|
|
+ "generic-ehci";
|
|
+ reg = <0x4101000 0x100>;
|
|
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_OHCI0>,
|
|
+ <&ccu CLK_BUS_EHCI0>,
|
|
+ <&ccu CLK_USB_OHCI0>;
|
|
+ resets = <&ccu RST_BUS_OHCI0>,
|
|
+ <&ccu RST_BUS_EHCI0>;
|
|
+ phys = <&usbphy 0>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ohci0: usb@4101400 {
|
|
+ compatible = "allwinner,sun20i-d1-ohci",
|
|
+ "generic-ohci";
|
|
+ reg = <0x4101400 0x100>;
|
|
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_OHCI0>,
|
|
+ <&ccu CLK_USB_OHCI0>;
|
|
+ resets = <&ccu RST_BUS_OHCI0>;
|
|
+ phys = <&usbphy 0>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ehci1: usb@4200000 {
|
|
+ compatible = "allwinner,sun20i-d1-ehci",
|
|
+ "generic-ehci";
|
|
+ reg = <0x4200000 0x100>;
|
|
+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_OHCI1>,
|
|
+ <&ccu CLK_BUS_EHCI1>,
|
|
+ <&ccu CLK_USB_OHCI1>;
|
|
+ resets = <&ccu RST_BUS_OHCI1>,
|
|
+ <&ccu RST_BUS_EHCI1>;
|
|
+ phys = <&usbphy 1>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ohci1: usb@4200400 {
|
|
+ compatible = "allwinner,sun20i-d1-ohci",
|
|
+ "generic-ohci";
|
|
+ reg = <0x4200400 0x100>;
|
|
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_OHCI1>,
|
|
+ <&ccu CLK_USB_OHCI1>;
|
|
+ resets = <&ccu RST_BUS_OHCI1>;
|
|
+ phys = <&usbphy 1>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ emac: ethernet@4500000 {
|
|
+ compatible = "allwinner,sun20i-d1-emac",
|
|
+ "allwinner,sun50i-a64-emac";
|
|
+ reg = <0x4500000 0x10000>;
|
|
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+ clocks = <&ccu CLK_BUS_EMAC>;
|
|
+ clock-names = "stmmaceth";
|
|
+ resets = <&ccu RST_BUS_EMAC>;
|
|
+ reset-names = "stmmaceth";
|
|
+ syscon = <&syscon>;
|
|
+ status = "disabled";
|
|
+
|
|
+ mdio: mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ display_clocks: clock-controller@5000000 {
|
|
+ compatible = "allwinner,sun20i-d1-de2-clk",
|
|
+ "allwinner,sun50i-h5-de2-clk";
|
|
+ reg = <0x5000000 0x10000>;
|
|
+ clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
|
|
+ clock-names = "bus", "mod";
|
|
+ resets = <&ccu RST_BUS_DE>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ mixer0: mixer@5100000 {
|
|
+ compatible = "allwinner,sun20i-d1-de2-mixer-0";
|
|
+ reg = <0x5100000 0x100000>;
|
|
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
|
|
+ <&display_clocks CLK_MIXER0>;
|
|
+ clock-names = "bus", "mod";
|
|
+ resets = <&display_clocks RST_MIXER0>;
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ mixer0_out: port@1 {
|
|
+ reg = <1>;
|
|
+
|
|
+ mixer0_out_tcon_top_mixer0: endpoint {
|
|
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mixer1: mixer@5200000 {
|
|
+ compatible = "allwinner,sun20i-d1-de2-mixer-1";
|
|
+ reg = <0x5200000 0x100000>;
|
|
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
|
|
+ <&display_clocks CLK_MIXER1>;
|
|
+ clock-names = "bus", "mod";
|
|
+ resets = <&display_clocks RST_MIXER1>;
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ mixer1_out: port@1 {
|
|
+ reg = <1>;
|
|
+
|
|
+ mixer1_out_tcon_top_mixer1: endpoint {
|
|
+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_top: tcon-top@5460000 {
|
|
+ compatible = "allwinner,sun20i-d1-tcon-top";
|
|
+ reg = <0x5460000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_DPSS_TOP>,
|
|
+ <&ccu CLK_TCON_TV>,
|
|
+ <&ccu CLK_TVE>,
|
|
+ <&ccu CLK_TCON_LCD0>;
|
|
+ clock-names = "bus", "tcon-tv0", "tve0", "dsi";
|
|
+ clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
|
|
+ resets = <&ccu RST_BUS_DPSS_TOP>;
|
|
+ #clock-cells = <1>;
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_top_mixer0_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_top_mixer0_out: port@1 {
|
|
+ reg = <1>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
|
|
+ };
|
|
+
|
|
+ tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
|
|
+ reg = <2>;
|
|
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_top_mixer1_in: port@2 {
|
|
+ reg = <2>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_top_mixer1_in_mixer1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_top_mixer1_out: port@3 {
|
|
+ reg = <3>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
|
|
+ };
|
|
+
|
|
+ tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
|
|
+ reg = <2>;
|
|
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_top_hdmi_in: port@4 {
|
|
+ reg = <4>;
|
|
+
|
|
+ tcon_top_hdmi_in_tcon_tv0: endpoint {
|
|
+ remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_top_hdmi_out: port@5 {
|
|
+ reg = <5>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_lcd0: lcd-controller@5461000 {
|
|
+ compatible = "allwinner,sun20i-d1-tcon-lcd";
|
|
+ reg = <0x5461000 0x1000>;
|
|
+ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_TCON_LCD0>,
|
|
+ <&ccu CLK_TCON_LCD0>;
|
|
+ clock-names = "ahb", "tcon-ch0";
|
|
+ clock-output-names = "tcon-pixel-clock";
|
|
+ resets = <&ccu RST_BUS_TCON_LCD0>,
|
|
+ <&ccu RST_BUS_LVDS0>;
|
|
+ reset-names = "lcd", "lvds";
|
|
+ #clock-cells = <0>;
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_lcd0_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
|
|
+ };
|
|
+
|
|
+ tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_lcd0_out: port@1 {
|
|
+ reg = <1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_tv0: lcd-controller@5470000 {
|
|
+ compatible = "allwinner,sun20i-d1-tcon-tv";
|
|
+ reg = <0x5470000 0x1000>;
|
|
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_TCON_TV>,
|
|
+ <&tcon_top CLK_TCON_TOP_TV0>;
|
|
+ clock-names = "ahb", "tcon-ch1";
|
|
+ resets = <&ccu RST_BUS_TCON_TV>;
|
|
+ reset-names = "lcd";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_tv0_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
|
|
+ };
|
|
+
|
|
+ tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tcon_tv0_out: port@1 {
|
|
+ reg = <1>;
|
|
+
|
|
+ tcon_tv0_out_tcon_top_hdmi: endpoint {
|
|
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ riscv_wdt: watchdog@6011000 {
|
|
+ compatible = "allwinner,sun20i-d1-wdt";
|
|
+ reg = <0x6011000 0x20>;
|
|
+ interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
|
|
+ clock-names = "hosc", "losc";
|
|
+ };
|
|
+
|
|
+ r_ccu: clock-controller@7010000 {
|
|
+ compatible = "allwinner,sun20i-d1-r-ccu";
|
|
+ reg = <0x7010000 0x400>;
|
|
+ clocks = <&osc24M>,
|
|
+ <&rtc CLK_OSC32K>,
|
|
+ <&rtc CLK_IOSC>,
|
|
+ <&ccu CLK_PLL_PERIPH0_DIV3>;
|
|
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ rtc: rtc@7090000 {
|
|
+ compatible = "allwinner,sun20i-d1-rtc",
|
|
+ "allwinner,sun50i-r329-rtc";
|
|
+ reg = <0x7090000 0x400>;
|
|
+ interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&r_ccu CLK_BUS_R_RTC>,
|
|
+ <&osc24M>,
|
|
+ <&r_ccu CLK_R_AHB>;
|
|
+ clock-names = "bus", "hosc", "ahb";
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ plic: interrupt-controller@10000000 {
|
|
+ compatible = "allwinner,sun20i-d1-plic",
|
|
+ "thead,c900-plic";
|
|
+ reg = <0x10000000 0x4000000>;
|
|
+ interrupts-extended = <&cpu0_intc 11>,
|
|
+ <&cpu0_intc 9>;
|
|
+ interrupt-controller;
|
|
+ riscv,ndev = <176>;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/riscv/dts/sunxi-u-boot.dtsi
|
|
@@ -0,0 +1,68 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
+
|
|
+#include "binman.dtsi"
|
|
+
|
|
+/ {
|
|
+ cpus {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&binman {
|
|
+ u-boot-sunxi-with-spl {
|
|
+ filename = "u-boot-sunxi-with-spl.bin";
|
|
+ pad-byte = <0xff>;
|
|
+
|
|
+ blob@0 {
|
|
+ filename = "spl/sunxi-spl.bin";
|
|
+ };
|
|
+
|
|
+ blob@1 {
|
|
+ filename = "u-boot.itb";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&ccu {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&mbus {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&mmc0_pins {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&osc24M {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&pio {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&uart0_pb8_pins {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
|
|
@@ -0,0 +1,19 @@
|
|
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
|
+/*
|
|
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
|
|
+#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
|
|
+
|
|
+#define CLK_R_AHB 0
|
|
+
|
|
+#define CLK_BUS_R_TIMER 2
|
|
+#define CLK_BUS_R_TWD 3
|
|
+#define CLK_BUS_R_PPU 4
|
|
+#define CLK_R_IR_RX 5
|
|
+#define CLK_BUS_R_IR_RX 6
|
|
+#define CLK_BUS_R_RTC 7
|
|
+#define CLK_BUS_R_CPUCFG 8
|
|
+
|
|
+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
|
|
@@ -0,0 +1,16 @@
|
|
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
|
+/*
|
|
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
|
|
+#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
|
|
+
|
|
+#define RST_BUS_R_TIMER 0
|
|
+#define RST_BUS_R_TWD 1
|
|
+#define RST_BUS_R_PPU 2
|
|
+#define RST_BUS_R_IR_RX 3
|
|
+#define RST_BUS_R_RTC 4
|
|
+#define RST_BUS_R_CPUCFG 5
|
|
+
|
|
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */
|