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147 lines
4.3 KiB
Diff
147 lines
4.3 KiB
Diff
From 9796f3807764567ecde6e3787a66e4b4edbc35df Mon Sep 17 00:00:00 2001
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From: Jes Sorensen <Jes.Sorensen@redhat.com>
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Date: Fri, 22 Jul 2016 11:40:13 -0400
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Subject: [PATCH] rtl8xxxu: Implement rtl8188eu_config_channel()
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The 8188eu doesn't seem to have REG_FPGA0_ANALOG2, so implement it's
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own specific version.
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Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
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---
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 117 +++++++++++++++++++++
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1 file changed, 117 insertions(+)
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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@@ -283,6 +283,122 @@ static struct rtl8xxxu_rfregval rtl8188e
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{0xff, 0xffffffff}
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};
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+void rtl8188eu_config_channel(struct ieee80211_hw *hw)
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+{
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+ struct rtl8xxxu_priv *priv = hw->priv;
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+ u32 val32, rsr;
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+ u8 val8, opmode;
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+ bool ht = true;
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+ int sec_ch_above, channel;
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+ int i;
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+
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+ opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
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+ rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
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+ channel = hw->conf.chandef.chan->hw_value;
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+
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+ switch (hw->conf.chandef.width) {
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+ case NL80211_CHAN_WIDTH_20_NOHT:
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+ ht = false;
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+ case NL80211_CHAN_WIDTH_20:
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+ opmode |= BW_OPMODE_20MHZ;
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+ rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
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+
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+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
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+ val32 &= ~FPGA_RF_MODE;
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+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
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+
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+ val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
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+ val32 &= ~FPGA_RF_MODE;
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+ rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
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+ break;
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+ case NL80211_CHAN_WIDTH_40:
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+ if (hw->conf.chandef.center_freq1 >
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+ hw->conf.chandef.chan->center_freq) {
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+ sec_ch_above = 1;
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+ channel += 2;
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+ } else {
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+ sec_ch_above = 0;
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+ channel -= 2;
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+ }
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+
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+ opmode &= ~BW_OPMODE_20MHZ;
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+ rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
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+ rsr &= ~RSR_RSC_BANDWIDTH_40M;
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+ if (sec_ch_above)
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+ rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
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+ else
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+ rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
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+ rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
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+
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+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
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+ val32 |= FPGA_RF_MODE;
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+ rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
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+
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+ val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
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+ val32 |= FPGA_RF_MODE;
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+ rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
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+
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+ /*
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+ * Set Control channel to upper or lower. These settings
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+ * are required only for 40MHz
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+ */
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+ val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
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+ val32 &= ~CCK0_SIDEBAND;
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+ if (!sec_ch_above)
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+ val32 |= CCK0_SIDEBAND;
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+ rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
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+
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+ val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
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+ val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
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+ if (sec_ch_above)
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+ val32 |= OFDM_LSTF_PRIME_CH_LOW;
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+ else
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+ val32 |= OFDM_LSTF_PRIME_CH_HIGH;
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+ rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
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+
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+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
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+ val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
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+ if (sec_ch_above)
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+ val32 |= FPGA0_PS_UPPER_CHANNEL;
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+ else
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+ val32 |= FPGA0_PS_LOWER_CHANNEL;
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+ rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
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+ break;
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+
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+ default:
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+ break;
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+ }
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+
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+ for (i = RF_A; i < priv->rf_paths; i++) {
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+ val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
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+ val32 &= ~MODE_AG_CHANNEL_MASK;
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+ val32 |= channel;
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+ rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
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+ }
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+
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+ if (ht)
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+ val8 = 0x0e;
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+ else
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+ val8 = 0x0a;
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+
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+#if 0
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+ rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
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+ rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
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+
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+ rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
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+ rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
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+#endif
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+
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+ for (i = RF_A; i < priv->rf_paths; i++) {
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+ val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
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+ if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
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+ val32 &= ~MODE_AG_CHANNEL_20MHZ;
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+ else
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+ val32 |= MODE_AG_CHANNEL_20MHZ;
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+ rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
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+ }
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+}
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+
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static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv)
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{
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struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu;
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@@ -1009,6 +1125,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
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.init_phy_bb = rtl8188eu_init_phy_bb,
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.init_phy_rf = rtl8188eu_init_phy_rf,
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.phy_iq_calibrate = rtl8188eu_phy_iq_calibrate,
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+ .config_channel = rtl8188eu_config_channel,
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.parse_rx_desc = rtl8xxxu_parse_rxdesc16,
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.usb_quirks = rtl8188e_usb_quirks,
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.writeN_block_size = 128,
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