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0ea329fec4
Weijie Gao has submitted an updated version of the patchset adding support for MT7986 and MT7981 to U-Boot. Use that v2 patchset. Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image (was already fixed in OpenWrt) - Fix coding style - Minor changes https://patchwork.ozlabs.org/project/uboot/list/?series=316148 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
47 lines
1.4 KiB
Diff
47 lines
1.4 KiB
Diff
From 0a2cd71e3b16eaa8797b5eec78356970186e552e Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 31 Aug 2022 19:05:11 +0800
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Subject: [PATCH 25/32] clk: mediatek: add CLK_XTAL support for clock driver
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This adds the CLK_XTAL macro/flag to allow modeling clocks which are
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directly connected to the xtal clock.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/clk/mediatek/clk-mtk.c | 4 ++++
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drivers/clk/mediatek/clk-mtk.h | 3 ++-
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2 files changed, 6 insertions(+), 1 deletion(-)
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--- a/drivers/clk/mediatek/clk-mtk.c
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+++ b/drivers/clk/mediatek/clk-mtk.c
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@@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rat
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
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break;
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+ case CLK_PARENT_XTAL:
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default:
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rate = priv->tree->xtal_rate;
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}
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@@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rat
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
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priv->parent);
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break;
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+ case CLK_PARENT_XTAL:
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+ rate = priv->tree->xtal_rate;
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+ break;
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default:
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
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}
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--- a/drivers/clk/mediatek/clk-mtk.h
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -29,7 +29,8 @@
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#define CLK_PARENT_APMIXED BIT(4)
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#define CLK_PARENT_TOPCKGEN BIT(5)
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#define CLK_PARENT_INFRASYS BIT(6)
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-#define CLK_PARENT_MASK GENMASK(6, 4)
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+#define CLK_PARENT_XTAL BIT(7)
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+#define CLK_PARENT_MASK GENMASK(7, 4)
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#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
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