mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
e0e74d8a2c
swig has been installed on the buildbots a while a ago and Petr Štetiar got a fix for the pylibfdt error. Use that and re-enable the builds for mt7620 and mt7621. Refresh patches while at it. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
429 lines
11 KiB
Diff
429 lines
11 KiB
Diff
From b1549087ecd1eb53f6173b17b473134fd6cca157 Mon Sep 17 00:00:00 2001
|
|
From: Weijie Gao <weijie.gao@mediatek.com>
|
|
Date: Fri, 20 May 2022 11:22:26 +0800
|
|
Subject: [PATCH 06/25] mips: mtmips: add two reference boards for mt7621
|
|
|
|
The mt7621_rfb board supports integrated giga PHYs plus one external
|
|
giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1
|
|
slots, SDXC and USB.
|
|
|
|
The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it
|
|
uses NAND flash and SDXC is not available.
|
|
|
|
Reviewed-by: Stefan Roese <sr@denx.de>
|
|
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
|
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
|
|
---
|
|
arch/mips/dts/Makefile | 2 +
|
|
arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 +++++++++++++++++
|
|
arch/mips/dts/mediatek,mt7621-rfb.dts | 82 +++++++++++++++++++++
|
|
arch/mips/mach-mtmips/mt7621/Kconfig | 20 +++++
|
|
board/mediatek/mt7621/MAINTAINERS | 8 ++
|
|
board/mediatek/mt7621/Makefile | 3 +
|
|
board/mediatek/mt7621/board.c | 6 ++
|
|
configs/mt7621_nand_rfb_defconfig | 85 ++++++++++++++++++++++
|
|
configs/mt7621_rfb_defconfig | 82 +++++++++++++++++++++
|
|
9 files changed, 355 insertions(+)
|
|
create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts
|
|
create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts
|
|
create mode 100644 board/mediatek/mt7621/MAINTAINERS
|
|
create mode 100644 board/mediatek/mt7621/Makefile
|
|
create mode 100644 board/mediatek/mt7621/board.c
|
|
create mode 100644 configs/mt7621_nand_rfb_defconfig
|
|
create mode 100644 configs/mt7621_rfb_defconfig
|
|
|
|
--- a/arch/mips/dts/Makefile
|
|
+++ b/arch/mips/dts/Makefile
|
|
@@ -16,6 +16,8 @@ dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) +=
|
|
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
|
|
dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
|
|
dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
|
|
+dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb
|
|
+dtb-$(CONFIG_BOARD_MT7621_NAND_RFB) += mediatek,mt7621-nand-rfb.dtb
|
|
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
|
|
dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
|
|
dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
|
|
--- /dev/null
|
|
+++ b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
|
|
@@ -0,0 +1,67 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
|
|
+ *
|
|
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "mt7621.dtsi"
|
|
+
|
|
+/ {
|
|
+ compatible = "mediatek,mt7621-nand-rfb", "mediatek,mt7621-soc";
|
|
+ model = "MediaTek MT7621 RFB (NAND)";
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart0;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = &uart0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ state_default: pin_state {
|
|
+ nand {
|
|
+ groups = "spi", "sdxc";
|
|
+ function = "nand";
|
|
+ };
|
|
+
|
|
+ gpios {
|
|
+ groups = "i2c", "uart3", "pcie reset";
|
|
+ function = "gpio";
|
|
+ };
|
|
+
|
|
+ wdt {
|
|
+ groups = "wdt";
|
|
+ function = "wdt rst";
|
|
+ };
|
|
+
|
|
+ jtag {
|
|
+ groups = "jtag";
|
|
+ function = "jtag";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gpio {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+ð {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ssusb {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u3phy {
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/mips/dts/mediatek,mt7621-rfb.dts
|
|
@@ -0,0 +1,82 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
|
|
+ *
|
|
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "mt7621.dtsi"
|
|
+
|
|
+/ {
|
|
+ compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
|
|
+ model = "MediaTek MT7621 RFB (SPI-NOR)";
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart0;
|
|
+ spi0 = &spi;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = &uart0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ state_default: pin_state {
|
|
+ gpios {
|
|
+ groups = "i2c", "uart3", "pcie reset";
|
|
+ function = "gpio";
|
|
+ };
|
|
+
|
|
+ wdt {
|
|
+ groups = "wdt";
|
|
+ function = "wdt rst";
|
|
+ };
|
|
+
|
|
+ jtag {
|
|
+ groups = "jtag";
|
|
+ function = "jtag";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gpio {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spi {
|
|
+ status = "okay";
|
|
+ num-cs = <2>;
|
|
+
|
|
+ spi-flash@0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "jedec,spi-nor";
|
|
+ spi-max-frequency = <25000000>;
|
|
+ reg = <0>;
|
|
+ };
|
|
+};
|
|
+
|
|
+ð {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mmc {
|
|
+ cap-sd-highspeed;
|
|
+
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ssusb {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u3phy {
|
|
+ status = "okay";
|
|
+};
|
|
--- a/arch/mips/mach-mtmips/mt7621/Kconfig
|
|
+++ b/arch/mips/mach-mtmips/mt7621/Kconfig
|
|
@@ -79,6 +79,26 @@ config MT7621_BOOT_FROM_NAND
|
|
choice
|
|
prompt "Board select"
|
|
|
|
+config BOARD_MT7621_RFB
|
|
+ bool "MediaTek MT7621 RFB (SPI-NOR)"
|
|
+ help
|
|
+ The reference design of MT7621A (WS3010) booting from SPI-NOR flash.
|
|
+ The board can be configured with DDR2 (64MiB~256MiB) or DDR3
|
|
+ (128MiB~512MiB). The board has 16 MiB SPI-NOR flash, built-in MT7530
|
|
+ GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 1 SDXC, 3 PCIe
|
|
+ sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
|
|
+ JTAG pins and expansion GPIO pins.
|
|
+
|
|
+config BOARD_MT7621_NAND_RFB
|
|
+ bool "MediaTek MT7621 RFB (NAND)"
|
|
+ help
|
|
+ The reference design of MT7621A (WS3010) booting from NAND flash.
|
|
+ The board can be configured with DDR2 (64MiB~256MiB) or DDR3
|
|
+ (128MiB~512MiB). The board has 128 MiB parallel NAND flash, built-in
|
|
+ MT7530 GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 3 PCIe
|
|
+ sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
|
|
+ JTAG pins and expansion GPIO pins.
|
|
+
|
|
endchoice
|
|
|
|
config SYS_CONFIG_NAME
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7621/MAINTAINERS
|
|
@@ -0,0 +1,8 @@
|
|
+MT7621_RFB BOARD
|
|
+M: Weijie Gao <weijie.gao@mediatek.com>
|
|
+S: Maintained
|
|
+F: board/mediatek/mt7621
|
|
+F: configs/mt7621_rfb_defconfig
|
|
+F: configs/mt7621_nand_rfb_defconfig
|
|
+F: arch/mips/dts/mediatek,mt7621-rfb.dts
|
|
+F: arch/mips/dts/mediatek,mt7621-nand-rfb.dts
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7621/Makefile
|
|
@@ -0,0 +1,3 @@
|
|
+# SPDX-License-Identifier: GPL-2.0
|
|
+
|
|
+obj-y += board.o
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7621/board.c
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
|
|
+ *
|
|
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
|
|
+ */
|
|
--- /dev/null
|
|
+++ b/configs/mt7621_nand_rfb_defconfig
|
|
@@ -0,0 +1,85 @@
|
|
+CONFIG_MIPS=y
|
|
+CONFIG_SYS_MALLOC_LEN=0x100000
|
|
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
|
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_ENV_SIZE=0x1000
|
|
+CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-nand-rfb"
|
|
+CONFIG_SPL_SERIAL=y
|
|
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
|
|
+CONFIG_SPL=y
|
|
+CONFIG_DEBUG_UART_BASE=0xbe000c00
|
|
+CONFIG_DEBUG_UART_CLOCK=50000000
|
|
+CONFIG_SYS_LOAD_ADDR=0x83000000
|
|
+CONFIG_ARCH_MTMIPS=y
|
|
+CONFIG_SOC_MT7621=y
|
|
+CONFIG_MT7621_BOOT_FROM_NAND=y
|
|
+CONFIG_BOARD_MT7621_NAND_RFB=y
|
|
+# CONFIG_MIPS_CACHE_SETUP is not set
|
|
+# CONFIG_MIPS_CACHE_DISABLE is not set
|
|
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
|
|
+CONFIG_MIPS_BOOT_FDT=y
|
|
+CONFIG_DEBUG_UART=y
|
|
+CONFIG_FIT=y
|
|
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
|
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
|
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
|
+CONFIG_SPL_NAND_SUPPORT=y
|
|
+CONFIG_SPL_NAND_BASE=y
|
|
+CONFIG_SPL_NAND_IDENT=y
|
|
+# CONFIG_BOOTM_NETBSD is not set
|
|
+# CONFIG_BOOTM_PLAN9 is not set
|
|
+# CONFIG_BOOTM_RTEMS is not set
|
|
+# CONFIG_BOOTM_VXWORKS is not set
|
|
+# CONFIG_CMD_ELF is not set
|
|
+# CONFIG_CMD_XIMG is not set
|
|
+# CONFIG_CMD_CRC32 is not set
|
|
+# CONFIG_CMD_DM is not set
|
|
+# CONFIG_CMD_FLASH is not set
|
|
+CONFIG_CMD_GPIO=y
|
|
+# CONFIG_CMD_LOADS is not set
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_MTD=y
|
|
+CONFIG_CMD_PART=y
|
|
+# CONFIG_CMD_PINMUX is not set
|
|
+CONFIG_CMD_USB=y
|
|
+# CONFIG_CMD_NFS is not set
|
|
+CONFIG_CMD_FAT=y
|
|
+CONFIG_CMD_FS_GENERIC=y
|
|
+# CONFIG_SPL_DOS_PARTITION is not set
|
|
+# CONFIG_ISO_PARTITION is not set
|
|
+CONFIG_EFI_PARTITION=y
|
|
+# CONFIG_SPL_EFI_PARTITION is not set
|
|
+CONFIG_PARTITION_TYPE_GUID=y
|
|
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
|
+# CONFIG_I2C is not set
|
|
+# CONFIG_INPUT is not set
|
|
+CONFIG_MMC=y
|
|
+# CONFIG_MMC_QUIRKS is not set
|
|
+# CONFIG_MMC_HW_PARTITIONING is not set
|
|
+CONFIG_MMC_MTK=y
|
|
+CONFIG_MTD=y
|
|
+CONFIG_DM_MTD=y
|
|
+CONFIG_MTD_RAW_NAND=y
|
|
+CONFIG_NAND_MT7621=y
|
|
+CONFIG_SYS_NAND_ONFI_DETECTION=y
|
|
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
|
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
|
|
+CONFIG_MEDIATEK_ETH=y
|
|
+CONFIG_PHY=y
|
|
+CONFIG_PHY_MTK_TPHY=y
|
|
+CONFIG_DEBUG_UART_SHIFT=2
|
|
+CONFIG_SYSRESET=y
|
|
+CONFIG_SYSRESET_RESETCTL=y
|
|
+CONFIG_USB=y
|
|
+CONFIG_USB_XHCI_HCD=y
|
|
+CONFIG_USB_XHCI_MTK=y
|
|
+CONFIG_USB_STORAGE=y
|
|
+CONFIG_WDT=y
|
|
+CONFIG_WDT_MT7621=y
|
|
+CONFIG_FAT_WRITE=y
|
|
+# CONFIG_BINMAN_FDT is not set
|
|
+CONFIG_LZMA=y
|
|
+# CONFIG_GZIP is not set
|
|
+CONFIG_SPL_LZMA=y
|
|
--- /dev/null
|
|
+++ b/configs/mt7621_rfb_defconfig
|
|
@@ -0,0 +1,82 @@
|
|
+CONFIG_MIPS=y
|
|
+CONFIG_SYS_MALLOC_LEN=0x100000
|
|
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
|
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_ENV_SIZE=0x1000
|
|
+CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-rfb"
|
|
+CONFIG_SPL_SERIAL=y
|
|
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
|
|
+CONFIG_SPL=y
|
|
+CONFIG_DEBUG_UART_BASE=0xbe000c00
|
|
+CONFIG_DEBUG_UART_CLOCK=50000000
|
|
+CONFIG_SYS_LOAD_ADDR=0x83000000
|
|
+CONFIG_ARCH_MTMIPS=y
|
|
+CONFIG_SOC_MT7621=y
|
|
+# CONFIG_MIPS_CACHE_SETUP is not set
|
|
+# CONFIG_MIPS_CACHE_DISABLE is not set
|
|
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
|
|
+CONFIG_MIPS_BOOT_FDT=y
|
|
+CONFIG_DEBUG_UART=y
|
|
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
|
|
+CONFIG_FIT=y
|
|
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
|
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
|
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
|
+CONFIG_SPL_NOR_SUPPORT=y
|
|
+CONFIG_TPL=y
|
|
+# CONFIG_TPL_FRAMEWORK is not set
|
|
+# CONFIG_BOOTM_NETBSD is not set
|
|
+# CONFIG_BOOTM_PLAN9 is not set
|
|
+# CONFIG_BOOTM_RTEMS is not set
|
|
+# CONFIG_BOOTM_VXWORKS is not set
|
|
+# CONFIG_CMD_ELF is not set
|
|
+# CONFIG_CMD_XIMG is not set
|
|
+# CONFIG_CMD_CRC32 is not set
|
|
+# CONFIG_CMD_DM is not set
|
|
+CONFIG_CMD_GPIO=y
|
|
+# CONFIG_CMD_LOADS is not set
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_PART=y
|
|
+# CONFIG_CMD_PINMUX is not set
|
|
+CONFIG_CMD_SPI=y
|
|
+# CONFIG_CMD_NFS is not set
|
|
+CONFIG_DOS_PARTITION=y
|
|
+# CONFIG_SPL_DOS_PARTITION is not set
|
|
+# CONFIG_ISO_PARTITION is not set
|
|
+CONFIG_EFI_PARTITION=y
|
|
+# CONFIG_SPL_EFI_PARTITION is not set
|
|
+CONFIG_PARTITION_TYPE_GUID=y
|
|
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
|
+# CONFIG_I2C is not set
|
|
+# CONFIG_INPUT is not set
|
|
+CONFIG_MMC=y
|
|
+# CONFIG_MMC_QUIRKS is not set
|
|
+# CONFIG_MMC_HW_PARTITIONING is not set
|
|
+CONFIG_MMC_MTK=y
|
|
+CONFIG_SF_DEFAULT_SPEED=20000000
|
|
+CONFIG_SPI_FLASH_BAR=y
|
|
+CONFIG_SPI_FLASH_EON=y
|
|
+CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
+CONFIG_SPI_FLASH_ISSI=y
|
|
+CONFIG_SPI_FLASH_MACRONIX=y
|
|
+CONFIG_SPI_FLASH_SPANSION=y
|
|
+CONFIG_SPI_FLASH_STMICRO=y
|
|
+CONFIG_SPI_FLASH_WINBOND=y
|
|
+CONFIG_SPI_FLASH_XMC=y
|
|
+CONFIG_SPI_FLASH_XTX=y
|
|
+CONFIG_MEDIATEK_ETH=y
|
|
+CONFIG_PHY=y
|
|
+CONFIG_PHY_MTK_TPHY=y
|
|
+CONFIG_DEBUG_UART_SHIFT=2
|
|
+CONFIG_SPI=y
|
|
+CONFIG_MT7621_SPI=y
|
|
+CONFIG_SYSRESET=y
|
|
+CONFIG_SYSRESET_RESETCTL=y
|
|
+CONFIG_WDT=y
|
|
+CONFIG_WDT_MT7621=y
|
|
+# CONFIG_BINMAN_FDT is not set
|
|
+CONFIG_LZMA=y
|
|
+# CONFIG_GZIP is not set
|
|
+CONFIG_SPL_LZMA=y
|