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2cd32a3304
This PHY requires some extra programming to work reliably with all devices. Backport upstream fix for it. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
316 lines
10 KiB
Diff
316 lines
10 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Subject: [PATCH] net: phy: cherry-pick Broadcom drivers updates from v4.10
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This includes following upstream commits:
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5519da874ad0 net: phy: broadcom: Move bcm54xx_auxctl_{read, write} to common library
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b14995ac2527 net: phy: broadcom: Add BCM54810 PHY entry
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5b4e29005123 net: phy: broadcom: add bcm54xx_auxctl_read
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d92ead16be40 net: phy: broadcom: Add support for BCM54612E
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3cf25904fe46 net: phy: broadcom: Update Auxiliary Control Register macros
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Other commits were skipped as they depend on other changes like
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ETHTOOL_PHY_DOWNSHIFT & DOWNSHIFT_DEV_DISABLE and new APIs like
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get_sset_count.
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One exception was picking new regs from commit d06f78c4232d ("net: phy:
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broadcom: Add support code for downshift/Wirespeed").
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -77,7 +77,7 @@ config BROADCOM_PHY
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select BCM_NET_PHYLIB
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---help---
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Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
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- BCM5481 and BCM5482 PHYs.
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+ BCM5481, BCM54810 and BCM5482 PHYs.
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config BCM_CYGNUS_PHY
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tristate "Drivers for Broadcom Cygnus SoC internal PHY"
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--- a/drivers/net/phy/bcm-phy-lib.c
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+++ b/drivers/net/phy/bcm-phy-lib.c
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@@ -50,6 +50,23 @@ int bcm_phy_read_exp(struct phy_device *
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}
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EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
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+int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
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+{
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+ /* The register must be written to both the Shadow Register Select and
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+ * the Shadow Read Register Selector
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+ */
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+ phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
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+ regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
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+ return phy_read(phydev, MII_BCM54XX_AUX_CTL);
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+}
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+EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
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+
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+int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
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+{
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+ return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
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+}
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+EXPORT_SYMBOL(bcm54xx_auxctl_write);
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+
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int bcm_phy_write_misc(struct phy_device *phydev,
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u16 reg, u16 chl, u16 val)
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{
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--- a/drivers/net/phy/bcm-phy-lib.h
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+++ b/drivers/net/phy/bcm-phy-lib.h
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@@ -19,6 +19,9 @@
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int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
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int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
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+int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
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+int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
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+
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int bcm_phy_write_misc(struct phy_device *phydev,
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u16 reg, u16 chl, u16 value);
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int bcm_phy_read_misc(struct phy_device *phydev,
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--- a/drivers/net/phy/broadcom.c
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+++ b/drivers/net/phy/broadcom.c
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@@ -18,7 +18,7 @@
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/brcmphy.h>
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-
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+#include <linux/of.h>
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#define BRCM_PHY_MODEL(phydev) \
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((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
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@@ -30,9 +30,32 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
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MODULE_AUTHOR("Maciej W. Rozycki");
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MODULE_LICENSE("GPL");
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-static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
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+static int bcm54810_config(struct phy_device *phydev)
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{
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- return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
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+ int rc, val;
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+
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+ val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
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+ val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
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+ rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
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+ val);
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+ if (rc < 0)
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+ return rc;
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+
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+ val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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+ val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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+ val |= MII_BCM54XX_AUXCTL_MISC_WREN;
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+ rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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+ val);
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+ if (rc < 0)
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+ return rc;
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+
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+ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
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+ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
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+ rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
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+ if (rc < 0)
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+ return rc;
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+
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+ return 0;
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}
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/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
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@@ -207,6 +230,12 @@ static int bcm54xx_config_init(struct ph
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(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
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bcm54xx_adjust_rxrefclk(phydev);
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+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
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+ err = bcm54810_config(phydev);
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+ if (err)
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+ return err;
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+ }
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+
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bcm54xx_phydsp_config(phydev);
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return 0;
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@@ -304,6 +333,7 @@ static int bcm5482_read_status(struct ph
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static int bcm5481_config_aneg(struct phy_device *phydev)
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{
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+ struct device_node *np = phydev->dev.of_node;
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int ret;
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/* Aneg firsly. */
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@@ -334,6 +364,49 @@ static int bcm5481_config_aneg(struct ph
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phy_write(phydev, 0x18, reg);
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}
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+ if (of_property_read_bool(np, "enet-phy-lane-swap")) {
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+ /* Lane Swap - Undocumented register...magic! */
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+ ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
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+ 0x11B);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ return ret;
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+}
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+
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+static int bcm54612e_config_aneg(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ /* First, auto-negotiate. */
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+ ret = genphy_config_aneg(phydev);
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+
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+ /* Clear TX internal delay unless requested. */
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+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
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+ /* Disable TXD to GTXCLK clock delay (default set) */
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+ /* Bit 9 is the only field in shadow register 00011 */
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+ bcm_phy_write_shadow(phydev, 0x03, 0);
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+ }
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+
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+ /* Clear RX internal delay unless requested. */
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+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
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+ u16 reg;
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+
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+ /* Errata: reads require filling in the write selector field */
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+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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+ MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
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+ reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
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+ /* Disable RXD to RXC delay (default set) */
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+ reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
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+ /* Clear shadow selector field */
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+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
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+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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+ MII_BCM54XX_AUXCTL_MISC_WREN | reg);
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+ }
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+
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return ret;
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}
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@@ -488,6 +561,18 @@ static struct phy_driver broadcom_driver
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.config_intr = bcm_phy_config_intr,
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.driver = { .owner = THIS_MODULE },
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}, {
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+ .phy_id = PHY_ID_BCM54612E,
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+ .phy_id_mask = 0xfffffff0,
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+ .name = "Broadcom BCM54612E",
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+ .features = PHY_GBIT_FEATURES |
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+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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+ .config_init = bcm54xx_config_init,
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+ .config_aneg = bcm54612e_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = bcm_phy_ack_intr,
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+ .config_intr = bcm_phy_config_intr,
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+}, {
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.phy_id = PHY_ID_BCM54616S,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM54616S",
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@@ -527,6 +612,18 @@ static struct phy_driver broadcom_driver
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.config_intr = bcm_phy_config_intr,
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.driver = { .owner = THIS_MODULE },
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}, {
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+ .phy_id = PHY_ID_BCM54810,
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+ .phy_id_mask = 0xfffffff0,
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+ .name = "Broadcom BCM54810",
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+ .features = PHY_GBIT_FEATURES |
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+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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+ .config_init = bcm54xx_config_init,
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+ .config_aneg = bcm5481_config_aneg,
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+ .read_status = genphy_read_status,
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+ .ack_interrupt = bcm_phy_ack_intr,
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+ .config_intr = bcm_phy_config_intr,
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+}, {
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.phy_id = PHY_ID_BCM5482,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5482",
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@@ -612,9 +709,11 @@ static struct mdio_device_id __maybe_unu
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{ PHY_ID_BCM5411, 0xfffffff0 },
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{ PHY_ID_BCM5421, 0xfffffff0 },
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{ PHY_ID_BCM5461, 0xfffffff0 },
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+ { PHY_ID_BCM54612E, 0xfffffff0 },
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{ PHY_ID_BCM54616S, 0xfffffff0 },
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{ PHY_ID_BCM5464, 0xfffffff0 },
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{ PHY_ID_BCM5481, 0xfffffff0 },
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+ { PHY_ID_BCM54810, 0xfffffff0 },
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{ PHY_ID_BCM5482, 0xfffffff0 },
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{ PHY_ID_BCM50610, 0xfffffff0 },
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{ PHY_ID_BCM50610M, 0xfffffff0 },
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--- a/include/linux/brcmphy.h
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+++ b/include/linux/brcmphy.h
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@@ -13,11 +13,13 @@
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#define PHY_ID_BCM5241 0x0143bc30
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#define PHY_ID_BCMAC131 0x0143bc70
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#define PHY_ID_BCM5481 0x0143bca0
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+#define PHY_ID_BCM54810 0x03625d00
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#define PHY_ID_BCM5482 0x0143bcb0
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#define PHY_ID_BCM5411 0x00206070
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#define PHY_ID_BCM5421 0x002060e0
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#define PHY_ID_BCM5464 0x002060b0
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#define PHY_ID_BCM5461 0x002060c0
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+#define PHY_ID_BCM54612E 0x03625e60
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#define PHY_ID_BCM54616S 0x03625d10
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#define PHY_ID_BCM57780 0x03625d90
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@@ -55,6 +57,7 @@
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#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
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#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
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#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
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+
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/* Broadcom BCM7xxx specific workarounds */
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#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
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#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
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@@ -105,11 +108,14 @@
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#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
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#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
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+#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
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#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
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#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
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#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
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-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
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/*
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* Broadcom LED source encodings. These are used in BCM5461, BCM5481,
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@@ -124,6 +130,7 @@
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#define BCM_LED_SRC_INTR 0x6
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#define BCM_LED_SRC_QUALITY 0x7
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#define BCM_LED_SRC_RCVLED 0x8
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+#define BCM_LED_SRC_WIRESPEED 0x9
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#define BCM_LED_SRC_MULTICOLOR1 0xa
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#define BCM_LED_SRC_OPENSHORT 0xb
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#define BCM_LED_SRC_OFF 0xe /* Tied high */
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@@ -135,6 +142,14 @@
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* Shadow values go into bits [14:10] of register 0x1c to select a shadow
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* register to access.
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*/
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+
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+/* 00100: Reserved control register 2 */
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+#define BCM54XX_SHD_SCR2 0x04
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+#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
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+#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
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+#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
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+#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
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+
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/* 00101: Spare Control Register 3 */
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#define BCM54XX_SHD_SCR3 0x05
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#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
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@@ -189,6 +204,12 @@
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#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
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#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
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+/* BCM54810 Registers */
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+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
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+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
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+#define BCM54810_SHD_CLK_CTL 0x3
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+#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
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+
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/*****************************************************************************/
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/* Fast Ethernet Transceiver definitions. */
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