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openwrt/target/linux/bcm27xx/patches-6.6/950-0622-drm-vc4-Add-additional-warn_on.patch
John Audia 9af0e94fa6 kernel: bump 6.6 to 6.6.64 
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.64

Manually rebased:
	generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
	bcm27xx/patches-6.6/950-0585-drm-vc4-Introduce-generation-number-enum.patch
	bcm27xx/patches-6.6/950-0610-drm-vc4-hvs-Support-BCM2712-HVS.patch
	bcm27xx/patches-6.6/950-0829-vc4-hvs-Add-support-for-D0-register-changes.patch

Removed upstreamed:
	bcm27xx/patches-6.6/950-0597-drm-vc4-hdmi-Avoid-hang-with-debug-registers-when-su.patch[1]
	bcm27xx/patches-6.6/950-0599-drm-vc4-Fix-dlist-debug-not-resetting-the-next-entry.patch[2]
	bcm27xx/patches-6.6/950-0600-drm-vc4-Remove-incorrect-limit-from-hvs_dlist-debugf.patch[3]
	bcm27xx/patches-6.6/950-0708-drm-vc4-Correct-logic-on-stopping-an-HVS-channel.patch[4]
	ramips/patches-6.6/002-01-v6.13-clk-ralink-mtmips-fix-clock-plan-for-Ralink-SoC-RT38.patch[5]
	ramips/patches-6.6/002-02-v6.13-clk-ralink-mtmips-fix-clocks-probe-order-in-oldest-r.patch[6]

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=223ee2567a55e4f80315c768d2969e6a3b9fb23d
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=8182b5ca19c6f173b6498d1c6d3e4b034b76bbde
3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=52c1716f65a558174e381360bd88f18dae4be85c
4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=9728b508b01a5eeeac79ceb676364c674dd951ac
5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=f85a1d06afbcc57ac44176db8f9d7a934979952c
6. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=fbb13732c6ffa9d58cedafabcd5ce8fd7ef8ae5a

Build system: x86/64
Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3

Co-authored-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/17217
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 5158e28769)
2024-12-15 01:43:39 +01:00

241 lines
6.9 KiB
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Raw Blame History

From e667d11b9e6ee013b4d496b190816d3b63b4d703 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Tue, 21 Feb 2023 14:38:32 +0100
Subject: [PATCH 0622/1085] drm/vc4: Add additional warn_on
Some code path in vc4 are conditional to a generation and cannot be
executed on others. Let's put a WARN_ON if that ever happens.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_hvs.c | 32 ++++++++++++++++++++++++++++++--
drivers/gpu/drm/vc4/vc4_kms.c | 6 ++++++
drivers/gpu/drm/vc4/vc4_plane.c | 19 +++++++++++++++++++
3 files changed, 55 insertions(+), 2 deletions(-)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -417,12 +417,15 @@ static int vc4_hvs_upload_linear_kernel(
static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
struct vc4_crtc *vc4_crtc)
{
- struct drm_device *drm = &hvs->vc4->base;
+ struct vc4_dev *vc4 = hvs->vc4;
+ struct drm_device *drm = &vc4->base;
struct drm_crtc *crtc = &vc4_crtc->base;
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
int idx;
u32 i;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
+
if (!drm_dev_enter(drm, &idx))
return;
@@ -761,6 +764,8 @@ u8 vc4_hvs_get_fifo_frame_count(struct v
u8 field = 0;
int idx;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
+
if (!drm_dev_enter(drm, &idx))
return 0;
@@ -794,6 +799,8 @@ int vc4_hvs_get_fifo_from_output(struct
u32 reg;
int ret;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
+
switch (vc4->gen) {
case VC4_GEN_4:
return output;
@@ -883,6 +890,8 @@ static int vc4_hvs_init_channel(struct v
u32 dispctrl;
int idx;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
+
if (!drm_dev_enter(drm, &idx))
return -ENODEV;
@@ -950,6 +959,8 @@ static int vc6_hvs_init_channel(struct v
u32 disp_ctrl1;
int idx;
+ WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
+
if (!drm_dev_enter(drm, &idx))
return -ENODEV;
@@ -975,9 +986,12 @@ static int vc6_hvs_init_channel(struct v
static void __vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
{
- struct drm_device *drm = &hvs->vc4->base;
+ struct vc4_dev *vc4 = hvs->vc4;
+ struct drm_device *drm = &vc4->base;
int idx;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
+
if (!drm_dev_enter(drm, &idx))
return;
@@ -1008,6 +1022,8 @@ static void __vc6_hvs_stop_channel(struc
struct drm_device *drm = &vc4->base;
int idx;
+ WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
+
if (!drm_dev_enter(drm, &idx))
return;
@@ -1235,6 +1251,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
bool found = false;
int idx;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
+
if (!drm_dev_enter(dev, &idx)) {
vc4_crtc_send_vblank(crtc);
return;
@@ -1325,6 +1343,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
if (crtc->state->color_mgmt_changed) {
u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
+
if (crtc->state->gamma_lut) {
if (vc4->gen == VC4_GEN_4) {
vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
@@ -1365,6 +1385,8 @@ void vc4_hvs_mask_underrun(struct vc4_hv
u32 dispctrl;
int idx;
+ WARN_ON(vc4->gen > VC4_GEN_5);
+
if (!drm_dev_enter(drm, &idx))
return;
@@ -1385,6 +1407,8 @@ void vc4_hvs_unmask_underrun(struct vc4_
u32 dispctrl;
int idx;
+ WARN_ON(vc4->gen > VC4_GEN_5);
+
if (!drm_dev_enter(drm, &idx))
return;
@@ -1419,6 +1443,8 @@ static irqreturn_t vc4_hvs_irq_handler(i
u32 status;
u32 dspeislur;
+ WARN_ON(vc4->gen > VC4_GEN_5);
+
/*
* NOTE: We don't need to protect the register access using
* drm_dev_enter() there because the interrupt handler lifetime
@@ -1468,6 +1494,8 @@ static irqreturn_t vc6_hvs_eof_irq_handl
struct vc4_hvs *hvs = vc4->hvs;
unsigned int i;
+ WARN_ON(vc4->gen < VC4_GEN_6);
+
for (i = 0; i < HVS_NUM_CHANNELS; i++) {
if (!hvs->eof_irq[i].enabled)
continue;
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -141,6 +141,8 @@ vc4_ctm_commit(struct vc4_dev *vc4, stru
if (vc4->firmware_kms)
return;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
+
if (ctm_state->fifo) {
HVS_WRITE(SCALER_OLEDCOEF2,
VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
@@ -216,6 +218,8 @@ static void vc4_hvs_pv_muxing_commit(str
struct drm_crtc *crtc;
unsigned int i;
+ WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
+
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
@@ -259,6 +263,8 @@ static void vc5_hvs_pv_muxing_commit(str
unsigned int i;
u32 reg;
+ WARN_ON_ONCE(vc4->gen != VC4_GEN_5);
+
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -555,8 +555,11 @@ static int vc4_plane_setup_clipping_and_
static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
{
+ struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
u32 scale, recip;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
+
scale = src / dst;
/* The specs note that while the reciprocal would be defined
@@ -581,10 +584,13 @@ static void vc4_write_tpz(struct vc4_pla
static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst, u32 xy, int channel, int chroma_offset)
{
+ struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
u32 scale = src / dst;
s32 offset, offset2;
s32 phase;
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
+
/* Start the phase at 1/2 pixel from the 1st pixel at src_x.
1/4 pixel for YUV, plus the offset for chroma siting */
if (channel) {
@@ -801,8 +807,11 @@ static size_t vc6_upm_size(const struct
static void vc4_write_scaling_parameters(struct drm_plane_state *state,
int channel)
{
+ struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
+
/* Ch0 H-PPF Word 0: Scaling Parameters */
if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
vc4_write_ppf(vc4_state,
@@ -1040,6 +1049,11 @@ static const u32 colorspace_coeffs[2][DR
static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
{
+ struct drm_device *dev = state->state->dev;
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+ WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
+
if (!state->fb->format->has_alpha)
return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
SCALER_POS2_ALPHA_MODE);
@@ -1061,6 +1075,11 @@ static u32 vc4_hvs4_get_alpha_blend_mode
static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
{
+ struct drm_device *dev = state->state->dev;
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+ WARN_ON_ONCE(vc4->gen != VC4_GEN_5 && vc4->gen != VC4_GEN_6);
+
if (!state->fb->format->has_alpha)
return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,
SCALER5_CTL2_ALPHA_MODE);
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