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5568f47259
This brings back USRobotics USR8200 support to the IXP4xx target. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
94 lines
3.1 KiB
Diff
94 lines
3.1 KiB
Diff
From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Thu, 21 Sep 2023 00:12:42 +0200
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Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
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This makes it possible to provide basic clock output on pins
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14 and 15. The clocks are typically used by random electronics,
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not modeled in the device tree, so they just need to be provided
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on request.
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In order to not disturb old systems that require that the
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hardware defaults are kept in the clock setting bits, we only
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manipulate these if either device tree property is present.
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Once we know a device needs one of the clocks we can set it
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in the device tree.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
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1 file changed, 48 insertions(+), 1 deletion(-)
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--- a/drivers/gpio/gpio-ixp4xx.c
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+++ b/drivers/gpio/gpio-ixp4xx.c
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@@ -38,6 +38,18 @@
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#define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
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#define IXP4XX_GPIO_STYLE_SIZE 3
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+/*
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+ * Clock output control register defines.
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+ */
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+#define IXP4XX_GPCLK_CLK0DC_SHIFT 0
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+#define IXP4XX_GPCLK_CLK0TC_SHIFT 4
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+#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0)
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+#define IXP4XX_GPCLK_MUX14 BIT(8)
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+#define IXP4XX_GPCLK_CLK1DC_SHIFT 16
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+#define IXP4XX_GPCLK_CLK1TC_SHIFT 20
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+#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16)
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+#define IXP4XX_GPCLK_MUX15 BIT(24)
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+
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/**
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* struct ixp4xx_gpio - IXP4 GPIO state container
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* @dev: containing device for this instance
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@@ -203,6 +215,8 @@ static int ixp4xx_gpio_probe(struct plat
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struct ixp4xx_gpio *g;
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struct gpio_irq_chip *girq;
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struct device_node *irq_parent;
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+ bool clk_14, clk_15;
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+ u32 val;
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int ret;
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g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
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@@ -233,7 +247,40 @@ static int ixp4xx_gpio_probe(struct plat
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*/
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if (of_machine_is_compatible("dlink,dsm-g600-a") ||
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of_machine_is_compatible("iom,nas-100d"))
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- __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
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+ val = 0;
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+ else
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+ val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
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+
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+ /*
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+ * If either clock output is enabled explicitly in the device tree
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+ * we take full control of the clock by masking off all bits for
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+ * the clock control and selectively enabling them. Otherwise
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+ * we leave the hardware default settings.
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+ *
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+ * Enable clock outputs with default timings of requested clock.
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+ * If you need control over TC and DC, add these to the device
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+ * tree bindings and use them here.
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+ */
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+ clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
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+ clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
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+ if (clk_14 || clk_15) {
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+ val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
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+ val &= ~IXP4XX_GPCLK_CLK0_MASK;
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+ val &= ~IXP4XX_GPCLK_CLK1_MASK;
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+ if (clk_14) {
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+ val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
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+ val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
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+ val |= IXP4XX_GPCLK_MUX14;
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+ }
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+
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+ if (clk_15) {
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+ val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
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+ val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
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+ val |= IXP4XX_GPCLK_MUX15;
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+ }
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+ }
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+
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+ __raw_writel(val, g->base + IXP4XX_REG_GPCLK);
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/*
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* This is a very special big-endian ARM issue: when the IXP4xx is
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