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6876465875
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.
`md 0x10117014 1`
PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.
Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.
Also, added a kernel message to display the EPHY base address.
Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 0976b6c426)
108 lines
1.6 KiB
Plaintext
108 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7620a_iptime.dtsi"
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/ {
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compatible = "iptime,a1004ns", "ralink,mt7620a-soc";
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model = "ipTIME A1004ns";
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aliases {
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led-boot = &led_cpu;
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led-failsafe = &led_cpu;
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led-running = &led_cpu;
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led-upgrade = &led_cpu;
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};
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leds {
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compatible = "gpio-leds";
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led_cpu: cpu {
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label = "blue:cpu";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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};
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usb {
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label = "blue:usb";
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ohci_port1>, <&ehci_port1>;
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linux,default-trigger = "usbport";
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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};
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&firmware {
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reg = <0x30000 0xfd0000>;
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};
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&state_default {
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gpio {
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groups = "i2c", "uartf", "spi refclk";
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function = "gpio";
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &mdio_pins>;
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port@5 {
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status = "okay";
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mediatek,fixed-link = <1000 1 1 1>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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};
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ethernet-phy@1 {
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reg = <1>;
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phy-mode = "rgmii";
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};
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ethernet-phy@2 {
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reg = <2>;
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phy-mode = "rgmii";
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};
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ethernet-phy@3 {
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reg = <3>;
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phy-mode = "rgmii";
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};
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ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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ethernet-phy@1f {
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reg = <0x1f>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,ephy-base = /bits/ 8 <12>;
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};
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