mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
105 lines
2.2 KiB
Diff
105 lines
2.2 KiB
Diff
From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001
|
||
From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
|
||
Date: Wed, 27 Oct 2021 00:57:06 +0800
|
||
Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
|
||
MIME-Version: 1.0
|
||
Content-Type: text/plain; charset=UTF-8
|
||
Content-Transfer-Encoding: 8bit
|
||
|
||
Define the Realtek RTL8365MB switch without interrupt support on the device
|
||
tree of Asus RT-AC88U.
|
||
|
||
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
|
||
Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk>
|
||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||
---
|
||
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++
|
||
1 file changed, 77 insertions(+)
|
||
|
||
--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
|
||
+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
|
||
@@ -93,6 +93,83 @@
|
||
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
|
||
};
|
||
};
|
||
+
|
||
+ switch {
|
||
+ compatible = "realtek,rtl8365mb";
|
||
+ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
|
||
+ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
|
||
+ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
|
||
+ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
|
||
+ realtek,disable-leds;
|
||
+ dsa,member = <1 0>;
|
||
+
|
||
+ ports {
|
||
+ #address-cells = <1>;
|
||
+ #size-cells = <0>;
|
||
+ reg = <0>;
|
||
+
|
||
+ port@0 {
|
||
+ reg = <0>;
|
||
+ label = "lan5";
|
||
+ phy-handle = <ðphy0>;
|
||
+ };
|
||
+
|
||
+ port@1 {
|
||
+ reg = <1>;
|
||
+ label = "lan6";
|
||
+ phy-handle = <ðphy1>;
|
||
+ };
|
||
+
|
||
+ port@2 {
|
||
+ reg = <2>;
|
||
+ label = "lan7";
|
||
+ phy-handle = <ðphy2>;
|
||
+ };
|
||
+
|
||
+ port@3 {
|
||
+ reg = <3>;
|
||
+ label = "lan8";
|
||
+ phy-handle = <ðphy3>;
|
||
+ };
|
||
+
|
||
+ port@6 {
|
||
+ reg = <6>;
|
||
+ label = "cpu";
|
||
+ ethernet = <&sw0_p5>;
|
||
+ phy-mode = "rgmii";
|
||
+ tx-internal-delay-ps = <2000>;
|
||
+ rx-internal-delay-ps = <2000>;
|
||
+
|
||
+ fixed-link {
|
||
+ speed = <1000>;
|
||
+ full-duplex;
|
||
+ pause;
|
||
+ };
|
||
+ };
|
||
+ };
|
||
+
|
||
+ mdio {
|
||
+ compatible = "realtek,smi-mdio";
|
||
+ #address-cells = <1>;
|
||
+ #size-cells = <0>;
|
||
+
|
||
+ ethphy0: ethernet-phy@0 {
|
||
+ reg = <0>;
|
||
+ };
|
||
+
|
||
+ ethphy1: ethernet-phy@1 {
|
||
+ reg = <1>;
|
||
+ };
|
||
+
|
||
+ ethphy2: ethernet-phy@2 {
|
||
+ reg = <2>;
|
||
+ };
|
||
+
|
||
+ ethphy3: ethernet-phy@3 {
|
||
+ reg = <3>;
|
||
+ };
|
||
+ };
|
||
+ };
|
||
};
|
||
|
||
&srab {
|