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05ed7dc50d
Patches automatically rebased. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
66 lines
2.1 KiB
Diff
66 lines
2.1 KiB
Diff
From 44bb7c72cdd830f54fe18e730205f892d9cbfe39 Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Thu, 19 Nov 2020 17:43:08 +0200
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Subject: [PATCH 102/247] dt-bindings: clock: at91: add sama7g5 pll defines
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Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
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PMC_TYPE_CORE clock.
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Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/sama7g5.c | 6 +++---
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include/dt-bindings/clock/at91.h | 10 ++++++++++
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2 files changed, 13 insertions(+), 3 deletions(-)
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--- a/drivers/clk/at91/sama7g5.c
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+++ b/drivers/clk/at91/sama7g5.c
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@@ -182,13 +182,13 @@ static const struct {
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.p = "audiopll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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- .eid = PMC_I2S0_MUX, },
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+ .eid = PMC_AUDIOPMCPLL, },
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{ .n = "audiopll_diviock",
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.p = "audiopll_fracck",
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.l = &pll_layout_divio,
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.t = PLL_TYPE_DIV,
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- .eid = PMC_I2S1_MUX, },
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+ .eid = PMC_AUDIOIOPLL, },
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},
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[PLL_ID_ETH] = {
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@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(str
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if (IS_ERR(regmap))
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return;
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- sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
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+ sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
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nck(sama7g5_systemck),
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nck(sama7g5_periphck),
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nck(sama7g5_gck), 8);
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--- a/include/dt-bindings/clock/at91.h
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+++ b/include/dt-bindings/clock/at91.h
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@@ -25,6 +25,16 @@
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#define PMC_PLLBCK 8
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#define PMC_AUDIOPLLCK 9
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+/* SAMA7G5 */
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+#define PMC_CPUPLL (PMC_MAIN + 1)
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+#define PMC_SYSPLL (PMC_MAIN + 2)
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+#define PMC_DDRPLL (PMC_MAIN + 3)
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+#define PMC_IMGPLL (PMC_MAIN + 4)
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+#define PMC_BAUDPLL (PMC_MAIN + 5)
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+#define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
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+#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
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+#define PMC_ETHPLL (PMC_MAIN + 8)
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+
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#ifndef AT91_PMC_MOSCS
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#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
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#define AT91_PMC_LOCKA 1 /* PLLA Lock */
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