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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
93 lines
2.7 KiB
Diff
93 lines
2.7 KiB
Diff
From 8a2d9c6decdbd042b3475d5ab69c1a79f0fd54aa Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Mon, 21 Aug 2023 23:29:15 +0800
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Subject: [PATCH] clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by
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setting PLL0 rate to 1.5GHz
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CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
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But now PLL0 rate is 1GHz and the cpu frequency loads become
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333/500/500/1000MHz in fact.
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So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock
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and the divider of cpu_core before the setting.
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Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
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Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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.../clk/starfive/clk-starfive-jh7110-sys.c | 49 ++++++++++++++++++-
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1 file changed, 48 insertions(+), 1 deletion(-)
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--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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@@ -7,6 +7,7 @@
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*/
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#include <linux/auxiliary_bus.h>
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+#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/io.h>
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@@ -389,6 +390,7 @@ static int __init jh7110_syscrg_probe(st
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struct jh71x0_clk_priv *priv;
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unsigned int idx;
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int ret;
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+ struct clk *pllclk;
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priv = devm_kzalloc(&pdev->dev,
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struct_size(priv, reg, JH7110_SYSCLK_END),
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@@ -462,7 +464,52 @@ static int __init jh7110_syscrg_probe(st
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if (ret)
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return ret;
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- return jh7110_reset_controller_register(priv, "rst-sys", 0);
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+ ret = jh7110_reset_controller_register(priv, "rst-sys", 0);
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * Set PLL0 rate to 1.5GHz
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+ * In order to not affect the cpu when the PLL0 rate is changing,
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+ * we need to switch the parent of cpu_root clock to osc clock first,
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+ * and then switch back after setting the PLL0 rate.
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+ */
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+ pllclk = clk_get(priv->dev, "pll0_out");
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+ if (!IS_ERR(pllclk)) {
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+ struct clk *osc = clk_get(&pdev->dev, "osc");
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+ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
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+ struct clk *cpu_core = priv->reg[JH7110_SYSCLK_CPU_CORE].hw.clk;
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+
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+ if (IS_ERR(osc)) {
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+ clk_put(pllclk);
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+ return PTR_ERR(osc);
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+ }
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+
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+ /*
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+ * CPU need voltage regulation by CPUfreq if set 1.5GHz.
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+ * So in this driver, cpu_core need to be set the divider to be 2 first
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+ * and will be 750M after setting parent.
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+ */
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+ ret = clk_set_rate(cpu_core, clk_get_rate(cpu_core) / 2);
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+ if (ret)
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+ goto failed_set;
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+
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+ ret = clk_set_parent(cpu_root, osc);
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+ if (ret)
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+ goto failed_set;
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+
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+ ret = clk_set_rate(pllclk, 1500000000);
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+ if (ret)
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+ goto failed_set;
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+
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+ ret = clk_set_parent(cpu_root, pllclk);
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+
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+failed_set:
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+ clk_put(pllclk);
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+ clk_put(osc);
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+ }
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+
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+ return ret;
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}
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static const struct of_device_id jh7110_syscrg_match[] = {
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