mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 01:59:02 +00:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
114 lines
2.9 KiB
Diff
114 lines
2.9 KiB
Diff
From 944b96d734199642e2ede978c48d754109ca334c Mon Sep 17 00:00:00 2001
|
|
From: Xingyu Wu <xingyu.wu@starfivetech.com>
|
|
Date: Mon, 20 Mar 2023 21:54:31 +0800
|
|
Subject: [PATCH 059/122] dt-bindings: timer: Add timer for StarFive JH7110 SoC
|
|
|
|
Add bindings for the timer on the JH7110 RISC-V SoC
|
|
by StarFive Technology Ltd.
|
|
|
|
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
|
|
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
---
|
|
.../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
|
|
1 file changed, 95 insertions(+)
|
|
create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
|
|
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
|
|
@@ -0,0 +1,95 @@
|
|
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
+%YAML 1.2
|
|
+---
|
|
+$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
|
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
+
|
|
+title: StarFive JH7110 Timer
|
|
+maintainers:
|
|
+ - Xingyu Wu <xingyu.wu@starfivetech.com>
|
|
+ - Samin Guo <samin.guo@starfivetech.com>
|
|
+
|
|
+description:
|
|
+ This timer has four free-running 32 bit counters in StarFive JH7110 SoC.
|
|
+ And each channel(counter) triggers an interrupt when timeout. They support
|
|
+ one-shot mode and continuous-run mode.
|
|
+
|
|
+properties:
|
|
+ compatible:
|
|
+ const: starfive,jh7110-timer
|
|
+
|
|
+ reg:
|
|
+ maxItems: 1
|
|
+
|
|
+ interrupts:
|
|
+ items:
|
|
+ - description: channel 0
|
|
+ - description: channel 1
|
|
+ - description: channel 2
|
|
+ - description: channel 3
|
|
+
|
|
+ clocks:
|
|
+ items:
|
|
+ - description: timer APB
|
|
+ - description: channel 0
|
|
+ - description: channel 1
|
|
+ - description: channel 2
|
|
+ - description: channel 3
|
|
+
|
|
+ clock-names:
|
|
+ items:
|
|
+ - const: apb
|
|
+ - const: ch0
|
|
+ - const: ch1
|
|
+ - const: ch2
|
|
+ - const: ch3
|
|
+
|
|
+ resets:
|
|
+ items:
|
|
+ - description: timer APB
|
|
+ - description: channel 0
|
|
+ - description: channel 1
|
|
+ - description: channel 2
|
|
+ - description: channel 3
|
|
+
|
|
+ reset-names:
|
|
+ items:
|
|
+ - const: apb
|
|
+ - const: ch0
|
|
+ - const: ch1
|
|
+ - const: ch2
|
|
+ - const: ch3
|
|
+
|
|
+required:
|
|
+ - compatible
|
|
+ - reg
|
|
+ - interrupts
|
|
+ - clocks
|
|
+ - clock-names
|
|
+ - resets
|
|
+ - reset-names
|
|
+
|
|
+additionalProperties: false
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ timer@13050000 {
|
|
+ compatible = "starfive,jh7110-timer";
|
|
+ reg = <0x13050000 0x10000>;
|
|
+ interrupts = <69>, <70>, <71> ,<72>;
|
|
+ clocks = <&clk 124>,
|
|
+ <&clk 125>,
|
|
+ <&clk 126>,
|
|
+ <&clk 127>,
|
|
+ <&clk 128>;
|
|
+ clock-names = "apb", "ch0", "ch1",
|
|
+ "ch2", "ch3";
|
|
+ resets = <&rst 117>,
|
|
+ <&rst 118>,
|
|
+ <&rst 119>,
|
|
+ <&rst 120>,
|
|
+ <&rst 121>;
|
|
+ reset-names = "apb", "ch0", "ch1",
|
|
+ "ch2", "ch3";
|
|
+ };
|
|
+
|