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f2e1e156c0
This adds support for eBPF JIT for 32 bit targets and significantly improves correctness. Signed-off-by: Felix Fietkau <nbd@nbd.name>
121 lines
3.4 KiB
Diff
121 lines
3.4 KiB
Diff
From: Johan Almbladh <johan.almbladh@anyfinetworks.com>
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Date: Tue, 5 Oct 2021 18:54:06 +0200
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Subject: [PATCH] mips: bpf: Add JIT workarounds for CPU errata
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This patch adds workarounds for the following CPU errata to the MIPS
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eBPF JIT, if enabled in the kernel configuration.
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- R10000 ll/sc weak ordering
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- Loongson-3 ll/sc weak ordering
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- Loongson-2F jump hang
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The Loongson-2F nop errata is implemented in uasm, which the JIT uses,
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so no additional mitigations are needed for that.
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Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
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Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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---
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--- a/arch/mips/net/bpf_jit_comp.c
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+++ b/arch/mips/net/bpf_jit_comp.c
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@@ -404,6 +404,7 @@ void emit_alu_r(struct jit_context *ctx,
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/* Atomic read-modify-write (32-bit) */
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void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code)
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{
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+ LLSC_sync(ctx);
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emit(ctx, ll, MIPS_R_T9, off, dst);
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switch (code) {
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case BPF_ADD:
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@@ -420,18 +421,19 @@ void emit_atomic_r(struct jit_context *c
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break;
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}
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emit(ctx, sc, MIPS_R_T8, off, dst);
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- emit(ctx, beqz, MIPS_R_T8, -16);
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+ emit(ctx, LLSC_beqz, MIPS_R_T8, -16 - LLSC_offset);
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emit(ctx, nop); /* Delay slot */
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}
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/* Atomic compare-and-exchange (32-bit) */
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void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off)
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{
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+ LLSC_sync(ctx);
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emit(ctx, ll, MIPS_R_T9, off, dst);
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emit(ctx, bne, MIPS_R_T9, res, 12);
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emit(ctx, move, MIPS_R_T8, src); /* Delay slot */
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emit(ctx, sc, MIPS_R_T8, off, dst);
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- emit(ctx, beqz, MIPS_R_T8, -20);
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+ emit(ctx, LLSC_beqz, MIPS_R_T8, -20 - LLSC_offset);
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emit(ctx, move, res, MIPS_R_T9); /* Delay slot */
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clobber_reg(ctx, res);
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}
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--- a/arch/mips/net/bpf_jit_comp.h
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+++ b/arch/mips/net/bpf_jit_comp.h
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@@ -87,7 +87,7 @@ struct jit_context {
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};
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/* Emit the instruction if the JIT memory space has been allocated */
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-#define emit(ctx, func, ...) \
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+#define __emit(ctx, func, ...) \
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do { \
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if ((ctx)->target != NULL) { \
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u32 *p = &(ctx)->target[ctx->jit_index]; \
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@@ -95,6 +95,30 @@ do { \
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} \
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(ctx)->jit_index++; \
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} while (0)
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+#define emit(...) __emit(__VA_ARGS__)
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+
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+/* Workaround for R10000 ll/sc errata */
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+#ifdef CONFIG_WAR_R10000
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+#define LLSC_beqz beqzl
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+#else
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+#define LLSC_beqz beqz
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+#endif
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+
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+/* Workaround for Loongson-3 ll/sc errata */
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+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
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+#define LLSC_sync(ctx) emit(ctx, sync, 0)
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+#define LLSC_offset 4
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+#else
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+#define LLSC_sync(ctx)
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+#define LLSC_offset 0
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+#endif
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+
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+/* Workaround for Loongson-2F jump errata */
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+#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
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+#define JALR_MASK 0xffffffffcfffffffULL
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+#else
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+#define JALR_MASK (~0ULL)
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+#endif
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/*
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* Mark a BPF register as accessed, it needs to be
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--- a/arch/mips/net/bpf_jit_comp64.c
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+++ b/arch/mips/net/bpf_jit_comp64.c
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@@ -375,6 +375,7 @@ static void emit_atomic_r64(struct jit_c
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u8 t1 = MIPS_R_T6;
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u8 t2 = MIPS_R_T7;
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+ LLSC_sync(ctx);
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emit(ctx, lld, t1, off, dst);
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switch (code) {
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case BPF_ADD:
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@@ -391,7 +392,7 @@ static void emit_atomic_r64(struct jit_c
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break;
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}
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emit(ctx, scd, t2, off, dst);
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- emit(ctx, beqz, t2, -16);
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+ emit(ctx, LLSC_beqz, t2, -16 - LLSC_offset);
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emit(ctx, nop); /* Delay slot */
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}
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@@ -414,7 +415,7 @@ static int emit_call(struct jit_context
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push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0);
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/* Emit function call */
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- emit_mov_i64(ctx, tmp, addr);
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+ emit_mov_i64(ctx, tmp, addr & JALR_MASK);
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emit(ctx, jalr, MIPS_R_RA, tmp);
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emit(ctx, nop); /* Delay slot */
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