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This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
77 lines
1.9 KiB
Diff
77 lines
1.9 KiB
Diff
From 0b99a4626c7e148df128c6a8cb686d500431189b Mon Sep 17 00:00:00 2001
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From: Jia Jie Ho <jiajie.ho@starfivetech.com>
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Date: Tue, 17 Jan 2023 09:54:43 +0800
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Subject: [PATCH 101/122] dt-bindings: rng: Add StarFive TRNG module
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Add documentation to describe Starfive true random number generator
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module.
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Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
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Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
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Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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---
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.../bindings/rng/starfive,jh7110-trng.yaml | 55 +++++++++++++++++++
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1 file changed, 55 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
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@@ -0,0 +1,55 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive SoC TRNG Module
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+
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+maintainers:
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+ - Jia Jie Ho <jiajie.ho@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-trng
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: Hardware reference clock
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+ - description: AHB reference clock
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+
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+ clock-names:
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+ items:
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+ - const: hclk
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+ - const: ahb
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+
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+ resets:
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+ maxItems: 1
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+
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+ interrupts:
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+ maxItems: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+ - interrupts
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ rng: rng@1600C000 {
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+ compatible = "starfive,jh7110-trng";
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+ reg = <0x1600C000 0x4000>;
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+ clocks = <&clk 15>, <&clk 16>;
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+ clock-names = "hclk", "ahb";
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+ resets = <&reset 3>;
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+ interrupts = <30>;
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+ };
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+...
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