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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
157 lines
4.7 KiB
Diff
157 lines
4.7 KiB
Diff
From 70df2590923e262ce8bf2b4f497f3481511d4fd6 Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Thu, 18 May 2023 18:12:26 +0800
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Subject: [PATCH 053/122] dt-bindings: clock: Add StarFive JH7110
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Image-Signal-Process clock and reset generator
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Add bindings for the Image-Signal-Process clock and reset
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generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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.../clock/starfive,jh7110-ispcrg.yaml | 87 +++++++++++++++++++
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.../dt-bindings/clock/starfive,jh7110-crg.h | 18 ++++
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.../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++
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3 files changed, 121 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
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@@ -0,0 +1,87 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
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+
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+maintainers:
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+ - Xingyu Wu <xingyu.wu@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-ispcrg
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: ISP Top core
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+ - description: ISP Top Axi
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+ - description: NOC ISP Bus
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+ - description: external DVP
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+
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+ clock-names:
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+ items:
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+ - const: isp_top_core
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+ - const: isp_top_axi
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+ - const: noc_bus_isp_axi
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+ - const: dvp_clk
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+
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+ resets:
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+ items:
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+ - description: ISP Top core
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+ - description: ISP Top Axi
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+ - description: NOC ISP Bus
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+
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+ '#clock-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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+
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+ '#reset-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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+
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+ power-domains:
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+ maxItems: 1
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+ description:
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+ ISP domain power
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+ - '#clock-cells'
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+ - '#reset-cells'
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+ - power-domains
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
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+ #include <dt-bindings/power/starfive,jh7110-pmu.h>
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+ #include <dt-bindings/reset/starfive,jh7110-crg.h>
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+
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+ ispcrg: clock-controller@19810000 {
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+ compatible = "starfive,jh7110-ispcrg";
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+ reg = <0x19810000 0x10000>;
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+ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
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+ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
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+ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
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+ <&dvp_clk>;
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+ clock-names = "isp_top_core", "isp_top_axi",
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+ "noc_bus_isp_axi", "dvp_clk";
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+ resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
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+ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
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+ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ power-domains = <&pwrc JH7110_PD_ISP>;
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+ };
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--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
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+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
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@@ -258,4 +258,22 @@
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#define JH7110_STGCLK_END 29
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+/* ISPCRG clocks */
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+#define JH7110_ISPCLK_DOM4_APB_FUNC 0
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+#define JH7110_ISPCLK_MIPI_RX0_PXL 1
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+#define JH7110_ISPCLK_DVP_INV 2
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+#define JH7110_ISPCLK_M31DPHY_CFG_IN 3
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+#define JH7110_ISPCLK_M31DPHY_REF_IN 4
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+#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5
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+#define JH7110_ISPCLK_VIN_APB 6
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+#define JH7110_ISPCLK_VIN_SYS 7
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+#define JH7110_ISPCLK_VIN_PIXEL_IF0 8
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+#define JH7110_ISPCLK_VIN_PIXEL_IF1 9
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+#define JH7110_ISPCLK_VIN_PIXEL_IF2 10
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+#define JH7110_ISPCLK_VIN_PIXEL_IF3 11
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+#define JH7110_ISPCLK_VIN_P_AXI_WR 12
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+#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13
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+
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+#define JH7110_ISPCLK_END 14
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+
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
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--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
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+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
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@@ -179,4 +179,20 @@
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#define JH7110_STGRST_END 23
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+/* ISPCRG resets */
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+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
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+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
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+#define JH7110_ISPRST_M31DPHY_HW 2
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+#define JH7110_ISPRST_M31DPHY_B09_AON 3
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+#define JH7110_ISPRST_VIN_APB 4
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+#define JH7110_ISPRST_VIN_PIXEL_IF0 5
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+#define JH7110_ISPRST_VIN_PIXEL_IF1 6
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+#define JH7110_ISPRST_VIN_PIXEL_IF2 7
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+#define JH7110_ISPRST_VIN_PIXEL_IF3 8
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+#define JH7110_ISPRST_VIN_SYS 9
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+#define JH7110_ISPRST_VIN_P_AXI_RD 10
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+#define JH7110_ISPRST_VIN_P_AXI_WR 11
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+
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+#define JH7110_ISPRST_END 12
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+
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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