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The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
51 lines
1.9 KiB
Diff
51 lines
1.9 KiB
Diff
From 66372055ffda939ce52ddc64270079dd4f04d764 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Fri, 21 Apr 2023 22:00:16 +0100
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Subject: [PATCH 0468/1085] drm/vc4: hdmi: Increase MAI fifo dreq threshold
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Now we wait for write responses and have a burst
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size of 4, we can set the fifo threshold much higher.
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Set it to 28 (of the 32 entry size) to keep fifo
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fuller and reduce chance of underflow.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 18 +++++++++++++-----
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1 file changed, 13 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -2521,6 +2521,7 @@ static int vc4_hdmi_audio_prepare(struct
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{
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struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
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struct drm_device *drm = vc4_hdmi->connector.dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(drm);
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struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
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unsigned int sample_rate = params->sample_rate;
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unsigned int channels = params->channels;
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@@ -2579,11 +2580,18 @@ static int vc4_hdmi_audio_prepare(struct
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VC4_HDMI_AUDIO_PACKET_CEA_MASK);
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/* Set the MAI threshold */
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- HDMI_WRITE(HDMI_MAI_THR,
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- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
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- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
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- VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
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- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
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+ if (vc4->is_vc5)
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+ HDMI_WRITE(HDMI_MAI_THR,
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+ VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
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+ VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
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+ VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
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+ VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
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+ else
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+ HDMI_WRITE(HDMI_MAI_THR,
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+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
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+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
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+ VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
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+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
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HDMI_WRITE(HDMI_MAI_CONFIG,
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VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
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