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2cd00b5147
This patch backports "irq-realtek-rtl" driver to Kernel 5.10 from 5.12. "MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X" is used in OpenWrt, so update the dependency by the additional patch. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
212 lines
5.7 KiB
Diff
212 lines
5.7 KiB
Diff
From 9f3a0f34b84ad1b9a8f2bdae44b66f16685b2143 Mon Sep 17 00:00:00 2001
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From: Bert Vermeulen <bert@biot.com>
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Date: Fri, 22 Jan 2021 21:42:24 +0100
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Subject: irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller
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This is a standard IRQ driver with only status and mask registers.
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The mapping from SoC interrupts (18-31) to MIPS core interrupts is
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done via an interrupt-map in device tree.
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Signed-off-by: Bert Vermeulen <bert@biot.com>
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Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
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Acked-by: John Crispin <john@phrozen.org>
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Signed-off-by: Marc Zyngier <maz@kernel.org>
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Link: https://lore.kernel.org/r/20210122204224.509124-3-bert@biot.com
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---
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drivers/irqchip/Makefile | 1 +
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drivers/irqchip/irq-realtek-rtl.c | 180 ++++++++++++++++++++++++++++++++++++++
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2 files changed, 181 insertions(+)
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create mode 100644 drivers/irqchip/irq-realtek-rtl.c
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--- a/drivers/irqchip/Makefile
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+++ b/drivers/irqchip/Makefile
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@@ -114,3 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-l
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obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
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obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
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obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o
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+obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
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--- /dev/null
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+++ b/drivers/irqchip/irq-realtek-rtl.c
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@@ -0,0 +1,180 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
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+ * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
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+ * Copyright (C) 2020 John Crispin <john@phrozen.org>
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+ */
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+
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+#include <linux/of_irq.h>
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+#include <linux/irqchip.h>
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+#include <linux/spinlock.h>
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+#include <linux/of_address.h>
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+#include <linux/irqchip/chained_irq.h>
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+
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+/* Global Interrupt Mask Register */
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+#define RTL_ICTL_GIMR 0x00
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+/* Global Interrupt Status Register */
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+#define RTL_ICTL_GISR 0x04
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+/* Interrupt Routing Registers */
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+#define RTL_ICTL_IRR0 0x08
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+#define RTL_ICTL_IRR1 0x0c
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+#define RTL_ICTL_IRR2 0x10
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+#define RTL_ICTL_IRR3 0x14
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+
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+#define REG(x) (realtek_ictl_base + x)
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+
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+static DEFINE_RAW_SPINLOCK(irq_lock);
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+static void __iomem *realtek_ictl_base;
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+
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+static void realtek_ictl_unmask_irq(struct irq_data *i)
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+{
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+ unsigned long flags;
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+ u32 value;
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+
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+ raw_spin_lock_irqsave(&irq_lock, flags);
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+
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+ value = readl(REG(RTL_ICTL_GIMR));
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+ value |= BIT(i->hwirq);
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+ writel(value, REG(RTL_ICTL_GIMR));
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+
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+ raw_spin_unlock_irqrestore(&irq_lock, flags);
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+}
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+
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+static void realtek_ictl_mask_irq(struct irq_data *i)
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+{
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+ unsigned long flags;
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+ u32 value;
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+
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+ raw_spin_lock_irqsave(&irq_lock, flags);
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+
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+ value = readl(REG(RTL_ICTL_GIMR));
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+ value &= ~BIT(i->hwirq);
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+ writel(value, REG(RTL_ICTL_GIMR));
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+
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+ raw_spin_unlock_irqrestore(&irq_lock, flags);
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+}
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+
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+static struct irq_chip realtek_ictl_irq = {
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+ .name = "realtek-rtl-intc",
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+ .irq_mask = realtek_ictl_mask_irq,
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+ .irq_unmask = realtek_ictl_unmask_irq,
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+};
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+
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+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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+{
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+ irq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops irq_domain_ops = {
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+ .map = intc_map,
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+ .xlate = irq_domain_xlate_onecell,
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+};
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+
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+static void realtek_irq_dispatch(struct irq_desc *desc)
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+{
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+ struct irq_domain *domain;
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+ unsigned int pending;
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+
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+ chained_irq_enter(chip, desc);
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+ pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
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+ if (unlikely(!pending)) {
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+ spurious_interrupt();
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+ goto out;
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+ }
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+ domain = irq_desc_get_handler_data(desc);
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+ generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
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+
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+out:
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+ chained_irq_exit(chip, desc);
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+}
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+
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+/*
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+ * SoC interrupts are cascaded to MIPS CPU interrupts according to the
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+ * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
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+ * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts
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+ * thus go into 4 IRRs.
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+ */
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+static int __init map_interrupts(struct device_node *node, struct irq_domain *domain)
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+{
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+ struct device_node *cpu_ictl;
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+ const __be32 *imap;
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+ u32 imaplen, soc_int, cpu_int, tmp, regs[4];
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+ int ret, i, irr_regs[] = {
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+ RTL_ICTL_IRR3,
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+ RTL_ICTL_IRR2,
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+ RTL_ICTL_IRR1,
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+ RTL_ICTL_IRR0,
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+ };
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+ u8 mips_irqs_set;
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+
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+ ret = of_property_read_u32(node, "#address-cells", &tmp);
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+ if (ret || tmp)
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+ return -EINVAL;
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+
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+ imap = of_get_property(node, "interrupt-map", &imaplen);
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+ if (!imap || imaplen % 3)
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+ return -EINVAL;
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+
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+ mips_irqs_set = 0;
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+ memset(regs, 0, sizeof(regs));
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+ for (i = 0; i < imaplen; i += 3 * sizeof(u32)) {
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+ soc_int = be32_to_cpup(imap);
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+ if (soc_int > 31)
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+ return -EINVAL;
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+
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+ cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));
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+ if (!cpu_ictl)
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+ return -EINVAL;
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+ ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp);
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+ if (ret || tmp != 1)
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+ return -EINVAL;
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+ of_node_put(cpu_ictl);
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+
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+ cpu_int = be32_to_cpup(imap + 2);
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+ if (cpu_int > 7)
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+ return -EINVAL;
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+
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+ if (!(mips_irqs_set & BIT(cpu_int))) {
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+ irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch,
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+ domain);
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+ mips_irqs_set |= BIT(cpu_int);
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+ }
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+
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+ regs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32;
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+ imap += 3;
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+ }
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+
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+ for (i = 0; i < 4; i++)
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+ writel(regs[i], REG(irr_regs[i]));
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+
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+ return 0;
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+}
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+
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+static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent)
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+{
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+ struct irq_domain *domain;
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+ int ret;
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+
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+ realtek_ictl_base = of_iomap(node, 0);
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+ if (!realtek_ictl_base)
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+ return -ENXIO;
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+
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+ /* Disable all cascaded interrupts */
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+ writel(0, REG(RTL_ICTL_GIMR));
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+
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+ domain = irq_domain_add_simple(node, 32, 0,
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+ &irq_domain_ops, NULL);
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+
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+ ret = map_interrupts(node, domain);
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+ if (ret) {
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+ pr_err("invalid interrupt map\n");
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init);
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