mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 02:29:01 +00:00
1f818b09f8
This series of upstream patches properly implement a clock and reset driver for old ralink SoCs[1]. And it includes some related fixes[2] and improvements[3][4]. All patches have been merged into linux-next. They will be part of upcoming Linux 6.5. In order to switch to the new system controller driver, all clocks and resets properties in SoC dtsi have been updated, and kernel symbol "CONFIG_CLK_MTMIPS" have been added to the kernel config files. [1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com [2] https://lore.kernel.org/all/20230622-mips-ralink-clk-wuninitialized-v1-1-ea9041240d10@kernel.org [3] https://lore.kernel.org/all/OSYP286MB03120BABB25900E113ED42B7BC5CA@OSYP286MB0312.JPNP286.PROD.OUTLOOK.COM [4] https://lore.kernel.org/all/TYAP286MB03151148AF8C054621DD55C3BC23A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM Tested on Motorola MWR03 (MT7628) Tested on Haier HW-L1W (MT7620) Signed-off-by: Shiji Yang <yangshiji66@qq.com>
391 lines
6.6 KiB
Plaintext
391 lines
6.6 KiB
Plaintext
/dts-v1/;
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "ralink,mt7620n-soc";
|
|
|
|
aliases {
|
|
spi0 = &spi0;
|
|
spi1 = &spi1;
|
|
serial0 = &uartlite;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "mips,mips24KEc";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,57600";
|
|
};
|
|
|
|
cpuintc: cpuintc {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
};
|
|
|
|
palmbus: palmbus@10000000 {
|
|
compatible = "palmbus";
|
|
reg = <0x10000000 0x200000>;
|
|
ranges = <0x0 0x10000000 0x1FFFFF>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
sysc: syscon@0 {
|
|
compatible = "ralink,mt7620-sysc", "syscon";
|
|
reg = <0x0 0x100>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
timer: timer@100 {
|
|
compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
|
|
reg = <0x100 0x20>;
|
|
|
|
clocks = <&sysc 5>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <1>;
|
|
};
|
|
|
|
watchdog: watchdog@120 {
|
|
compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
|
|
reg = <0x120 0x10>;
|
|
|
|
clocks = <&sysc 6>;
|
|
|
|
resets = <&sysc 8>;
|
|
reset-names = "wdt";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <1>;
|
|
};
|
|
|
|
intc: intc@200 {
|
|
compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
|
|
reg = <0x200 0x100>;
|
|
|
|
resets = <&sysc 19>;
|
|
reset-names = "intc";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
};
|
|
|
|
memc: memc@300 {
|
|
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
|
|
reg = <0x300 0x100>;
|
|
|
|
resets = <&sysc 20>;
|
|
reset-names = "mc";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <3>;
|
|
};
|
|
|
|
gpio0: gpio@600 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x600 0x34>;
|
|
|
|
resets = <&sysc 13>;
|
|
reset-names = "pio";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <24>;
|
|
ralink,gpio-base = <0>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
20 24 28 2c
|
|
30 34 ];
|
|
};
|
|
|
|
gpio1: gpio@638 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x638 0x24>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <16>;
|
|
ralink,gpio-base = <24>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
10 14 18 1c
|
|
20 24 ];
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio2: gpio@660 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x660 0x24>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <32>;
|
|
ralink,gpio-base = <40>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
10 14 18 1c
|
|
20 24 ];
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio3: gpio@688 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x688 0x24>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <1>;
|
|
ralink,gpio-base = <72>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
10 14 18 1c
|
|
20 24 ];
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c: i2c@900 {
|
|
compatible = "ralink,rt2880-i2c";
|
|
reg = <0x900 0x100>;
|
|
|
|
clocks = <&sysc 8>;
|
|
|
|
resets = <&sysc 16>;
|
|
reset-names = "i2c";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c_pins>;
|
|
};
|
|
|
|
spi0: spi@b00 {
|
|
compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
|
|
reg = <0xb00 0x40>;
|
|
|
|
clocks = <&sysc 10>;
|
|
|
|
resets = <&sysc 18>;
|
|
reset-names = "spi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi_pins>;
|
|
};
|
|
|
|
spi1: spi@b40 {
|
|
compatible = "ralink,rt2880-spi";
|
|
reg = <0xb40 0x60>;
|
|
|
|
clocks = <&sysc 11>;
|
|
|
|
resets = <&sysc 18>;
|
|
reset-names = "spi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi_cs1>;
|
|
};
|
|
|
|
uartlite: uartlite@c00 {
|
|
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
|
reg = <0xc00 0x100>;
|
|
|
|
clocks = <&sysc 12>;
|
|
|
|
resets = <&sysc 19>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <12>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uartlite_pins>;
|
|
};
|
|
|
|
systick: systick@d00 {
|
|
compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
|
|
reg = <0xd00 0x10>;
|
|
|
|
resets = <&sysc 28>;
|
|
reset-names = "intc";
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <7>;
|
|
};
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "ralink,rt2880-pinmux";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&state_default>;
|
|
|
|
state_default: pinctrl0 {
|
|
};
|
|
|
|
ephy_pins: ephy {
|
|
ephy {
|
|
groups = "ephy";
|
|
function = "ephy";
|
|
};
|
|
};
|
|
|
|
spi_pins: spi_pins {
|
|
spi_pins {
|
|
groups = "spi";
|
|
function = "spi";
|
|
};
|
|
};
|
|
|
|
spi_cs1: spi1 {
|
|
spi1 {
|
|
groups = "spi refclk";
|
|
function = "spi refclk";
|
|
};
|
|
};
|
|
|
|
i2c_pins: i2c_pins {
|
|
i2c_pins {
|
|
groups = "i2c";
|
|
function = "i2c";
|
|
};
|
|
};
|
|
|
|
uartlite_pins: uartlite {
|
|
uart {
|
|
groups = "uartlite";
|
|
function = "uartlite";
|
|
};
|
|
};
|
|
};
|
|
|
|
usbphy: usbphy {
|
|
compatible = "mediatek,mt7620-usbphy";
|
|
#phy-cells = <0>;
|
|
|
|
ralink,sysctl = <&sysc>;
|
|
/* usb phy reset is only controled by RSTCTRL bit 25 */
|
|
resets = <&sysc 25>, <&sysc 22>;
|
|
reset-names = "host", "device";
|
|
};
|
|
|
|
ethernet: ethernet@10100000 {
|
|
compatible = "mediatek,mt7620-eth";
|
|
reg = <0x10100000 0x10000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <5>;
|
|
|
|
resets = <&sysc 21>, <&sysc 23>;
|
|
reset-names = "fe", "esw";
|
|
|
|
mediatek,switch = <&gsw>;
|
|
};
|
|
|
|
gsw: gsw@10110000 {
|
|
compatible = "mediatek,mt7620-gsw";
|
|
reg = <0x10110000 0x8000>;
|
|
|
|
resets = <&sysc 23>;
|
|
reset-names = "esw";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <17>;
|
|
};
|
|
|
|
ehci: ehci@101c0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "generic-ehci";
|
|
reg = <0x101c0000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <18>;
|
|
|
|
phys = <&usbphy>;
|
|
phy-names = "usb";
|
|
|
|
status = "disabled";
|
|
|
|
ehci_port1: port@1 {
|
|
reg = <1>;
|
|
#trigger-source-cells = <0>;
|
|
};
|
|
};
|
|
|
|
ohci: ohci@101c1000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "generic-ohci";
|
|
reg = <0x101c1000 0x1000>;
|
|
|
|
phys = <&usbphy>;
|
|
phy-names = "usb";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <18>;
|
|
|
|
status = "disabled";
|
|
|
|
ohci_port1: port@1 {
|
|
reg = <1>;
|
|
#trigger-source-cells = <0>;
|
|
};
|
|
};
|
|
|
|
wmac: wmac@10180000 {
|
|
compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
|
|
reg = <0x10180000 0x40000>;
|
|
|
|
clocks = <&sysc 13>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <6>;
|
|
|
|
ralink,eeprom = "soc_wmac.eeprom";
|
|
};
|
|
};
|