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https://github.com/openwrt/openwrt.git
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7a0af40e37
Removed upstreamed:
backport-5.10/850-v5.17-0004-PCI-aardvark-Clear-all-MSIs-at-setup.patch
pending-5.10/850-0002-PCI-aardvark-Fix-reading-MSI-interrupt-number.patch
All other patches automatically rebased.
Build system: x86_64
Build-tested: bcm2711/RPi4B
Signed-off-by: John Audia <therealgraysky@proton.me>
(cherry picked from commit b754b0c721)
174 lines
6.4 KiB
Diff
174 lines
6.4 KiB
Diff
From 68727b545332327b4c2f9c0f8d006be8970e7832 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 19 Feb 2021 14:22:22 +0100
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Subject: [PATCH] PCI: aardvark: Fix support for PME requester on emulated
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bridge
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Enable aardvark PME interrupt unconditionally by unmasking it and read PME
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requester ID to emulated bridge config space immediately after receiving
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interrupt.
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PME requester ID is stored in the PCIE_MSG_LOG_REG register, which contains
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the last inbound message. So when new inbound message is received by HW
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(including non-PM), the content in PCIE_MSG_LOG_REG register is replaced by
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a new value.
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PCIe specification mandates that subsequent PMEs are kept pending until the
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PME Status Register bit is cleared by software by writing a 1b.
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Support for masking/unmasking PME interrupt on emulated bridge via
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PCI_EXP_RTCTL_PMEIE bit is now implemented only in emulated bridge config
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space, to ensure that we do not miss any aardvark PME interrupt.
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Reading of PCI_EXP_RTCAP and PCI_EXP_RTSTA registers is simplified as final
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value is now always stored into emulated bridge config space by the
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interrupt handler, so there is no need to implement support for these
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registers in read_pcie callback.
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Clearing of W1C bit PCI_EXP_RTSTA_PME is now also simplified as it is done
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by pci-bridge-emul.c code for emulated bridge config space. So there is no
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need to implement support for clearing this bit in write_pcie callback.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 94 +++++++++++++++------------
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1 file changed, 52 insertions(+), 42 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -597,6 +597,11 @@ static void advk_pcie_setup_hw(struct ad
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reg &= ~PCIE_ISR0_MSI_INT_PENDING;
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advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
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+ /* Unmask PME interrupt for processing of PME requester */
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+ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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+ reg &= ~PCIE_MSG_PM_PME_MASK;
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+ advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
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+
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/* Enable summary interrupt for GIC SPI source */
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reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
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advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
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@@ -863,22 +868,11 @@ advk_pci_bridge_emul_pcie_conf_read(stru
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*value = PCI_EXP_SLTSTA_PDS << 16;
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return PCI_BRIDGE_EMUL_HANDLED;
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- case PCI_EXP_RTCTL: {
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- u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
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- *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE;
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- *value |= PCI_EXP_RTCAP_CRSVIS << 16;
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- return PCI_BRIDGE_EMUL_HANDLED;
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- }
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-
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- case PCI_EXP_RTSTA: {
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- u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
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- u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
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- *value = msglog >> 16;
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- if (isr0 & PCIE_MSG_PM_PME_MASK)
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- *value |= PCI_EXP_RTSTA_PME;
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- return PCI_BRIDGE_EMUL_HANDLED;
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- }
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+ /*
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+ * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need
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+ * to be handled here, because their values are stored in emulated
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+ * config space buffer, and we read them from there when needed.
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+ */
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case PCI_EXP_LNKCAP: {
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u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
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@@ -932,22 +926,19 @@ advk_pci_bridge_emul_pcie_conf_write(str
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advk_pcie_wait_for_retrain(pcie);
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break;
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- case PCI_EXP_RTCTL:
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- /* Only mask/unmask PME interrupt */
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- if (mask & PCI_EXP_RTCTL_PMEIE) {
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- u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- if (new & PCI_EXP_RTCTL_PMEIE)
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- val &= ~PCIE_MSG_PM_PME_MASK;
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- else
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- val |= PCIE_MSG_PM_PME_MASK;
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- advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
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- }
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+ case PCI_EXP_RTCTL: {
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+ u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl);
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+ /* Only emulation of PMEIE and CRSSVE bits is provided */
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+ rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE;
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+ bridge->pcie_conf.rootctl = cpu_to_le16(rootctl);
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break;
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+ }
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- case PCI_EXP_RTSTA:
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- if (new & PCI_EXP_RTSTA_PME)
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- advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
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- break;
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+ /*
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+ * PCI_EXP_RTSTA is also supported, but does not need to be handled
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+ * here, because its value is stored in emulated config space buffer,
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+ * and we write it there when needed.
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+ */
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case PCI_EXP_DEVCTL:
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case PCI_EXP_DEVCTL2:
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@@ -1452,6 +1443,34 @@ static void advk_pcie_remove_irq_domain(
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irq_domain_remove(pcie->irq_domain);
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}
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+static void advk_pcie_handle_pme(struct advk_pcie *pcie)
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+{
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+ u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;
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+ int virq;
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+
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+ advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
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+
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+ /*
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+ * PCIE_MSG_LOG_REG contains the last inbound message, so store
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+ * the requester ID only when PME was not asserted yet.
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+ * Also do not trigger PME interrupt when PME is still asserted.
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+ */
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+ if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) {
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+ pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME);
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+
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+ /*
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+ * Trigger PME interrupt only if PMEIE bit in Root Control is set.
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+ * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0.
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+ */
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+ if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))
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+ return;
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+
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+ virq = irq_find_mapping(pcie->irq_domain, 0);
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+ if (generic_handle_irq(virq) == -EINVAL)
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+ dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n");
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+ }
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+}
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+
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static void advk_pcie_handle_msi(struct advk_pcie *pcie)
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{
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u32 msi_val, msi_mask, msi_status, msi_idx;
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@@ -1488,18 +1507,9 @@ static void advk_pcie_handle_int(struct
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isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
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- /* Process PME interrupt */
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- if (isr0_status & PCIE_MSG_PM_PME_MASK) {
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- /*
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- * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ
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- * receiver by writing to the PCI_EXP_RTSTA register of emulated
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- * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ,
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- * so use PCIe interrupt 0.
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- */
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- virq = irq_find_mapping(pcie->irq_domain, 0);
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- if (generic_handle_irq(virq) == -EINVAL)
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- dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n");
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- }
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+ /* Process PME interrupt as the first one to do not miss PME requester id */
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+ if (isr0_status & PCIE_MSG_PM_PME_MASK)
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+ advk_pcie_handle_pme(pcie);
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/* Process ERR interrupt */
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if (isr0_status & PCIE_ISR0_ERR_MASK) {
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