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f10f009609
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 42313
183 lines
5.9 KiB
Diff
183 lines
5.9 KiB
Diff
From dd91dc4b9c55c8fa24738249214274442e2fcbd3 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Mon, 10 Feb 2014 18:35:47 +0800
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Subject: [PATCH] clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Allwinner A20/A31 clock module controls the transmit clock source
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and interface type of the GMAC ethernet controller. Model this as
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a single clock for GMAC drivers to use.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++++++
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drivers/clk/sunxi/clk-sunxi.c | 96 +++++++++++++++++++++++
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2 files changed, 126 insertions(+)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index c37c764..256a908 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -38,6 +38,7 @@ Required properties:
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
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"allwinner,sun7i-a20-out-clk" - for the external output clocks
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+ "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
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@@ -56,6 +57,9 @@ Required properties for all clocks:
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And "allwinner,*-usb-clk" clocks also require:
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- reset-cells : shall be set to 1
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+For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
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+dummy clocks at 25 MHz and 125 MHz, respectively. See example.
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+
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Clock consumers should specify the desired clocks they use with a
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"clocks" phandle cell. Consumers that are using a gated clock should
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provide an additional ID in their clock property. This ID is the
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@@ -102,3 +106,29 @@ mmc0_clk: clk@01c20088 {
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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+
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+mii_phy_tx_clk: clk@2 {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <25000000>;
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+ clock-output-names = "mii_phy_tx";
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+};
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+
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+gmac_int_tx_clk: clk@3 {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac_int_tx";
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+};
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+
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+gmac_clk: clk@01c20164 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun7i-a20-gmac-clk";
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+ reg = <0x01c20164 0x4>;
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+ /*
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+ * The first clock must be fixed at 25MHz;
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+ * the second clock must be fixed at 125MHz
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+ */
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+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
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+ clock-output-names = "gmac";
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+};
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index d4cf297..335c987 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -411,6 +411,102 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
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/**
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+ * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
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+ *
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+ * This clock looks something like this
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+ * ________________________
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+ * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
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+ * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
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+ * Ext. 125MHz RGMII TX clk >--|__divider__/ |
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+ * |________________________|
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+ *
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+ * The external 125 MHz reference is optional, i.e. GMAC can use its
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+ * internal TX clock just fine. The A31 GMAC clock module does not have
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+ * the divider controls for the external reference.
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+ *
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+ * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
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+ * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
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+ * select the appropriate source and gate/ungate the output to the PHY.
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+ *
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+ * Only the GMAC should use this clock. Altering the clock so that it doesn't
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+ * match the GMAC's operation parameters will result in the GMAC not being
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+ * able to send traffic out. The GMAC driver should set the clock rate and
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+ * enable/disable this clock to configure the required state. The clock
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+ * driver then responds by auto-reparenting the clock.
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+ */
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+
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+#define SUN7I_A20_GMAC_GPIT 2
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+#define SUN7I_A20_GMAC_MASK 0x3
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+#define SUN7I_A20_GMAC_PARENTS 2
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+
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+static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
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+{
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+ struct clk *clk;
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+ struct clk_mux *mux;
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+ struct clk_gate *gate;
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+ const char *clk_name = node->name;
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+ const char *parents[SUN7I_A20_GMAC_PARENTS];
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+ void *reg;
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+
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+ if (of_property_read_string(node, "clock-output-names", &clk_name))
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+ return;
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+
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+ /* allocate mux and gate clock structs */
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+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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+ if (!mux)
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+ return;
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+
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+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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+ if (!gate)
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+ goto free_mux;
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+
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+ /* gmac clock requires exactly 2 parents */
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+ parents[0] = of_clk_get_parent_name(node, 0);
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+ parents[1] = of_clk_get_parent_name(node, 1);
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+ if (!parents[0] || !parents[1])
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+ goto free_gate;
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+
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+ reg = of_iomap(node, 0);
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+ if (!reg)
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+ goto free_gate;
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+
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+ /* set up gate and fixed rate properties */
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+ gate->reg = reg;
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+ gate->bit_idx = SUN7I_A20_GMAC_GPIT;
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+ gate->lock = &clk_lock;
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+ mux->reg = reg;
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+ mux->mask = SUN7I_A20_GMAC_MASK;
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+ mux->flags = CLK_MUX_INDEX_BIT;
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+ mux->lock = &clk_lock;
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+
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+ clk = clk_register_composite(NULL, clk_name,
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+ parents, SUN7I_A20_GMAC_PARENTS,
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+ &mux->hw, &clk_mux_ops,
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+ NULL, NULL,
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+ &gate->hw, &clk_gate_ops,
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+ 0);
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+
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+ if (IS_ERR(clk))
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+ goto iounmap_reg;
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+
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+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+ clk_register_clkdev(clk, clk_name, NULL);
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+
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+ return;
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+
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+iounmap_reg:
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+ iounmap(reg);
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+free_gate:
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+ kfree(gate);
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+free_mux:
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+ kfree(mux);
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+}
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+CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
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+ sun7i_a20_gmac_clk_setup);
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+
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+
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+
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+/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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--
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2.0.3
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