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55be011a71
This backports GD SPI NAND support from nand/next to v5.10 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
34 lines
1.3 KiB
Diff
34 lines
1.3 KiB
Diff
From 620a988813403318023296b61228ee8f3fcdb8e0 Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Sun, 20 Mar 2022 17:59:59 +0800
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Subject: [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG
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This chip is the 1.8v version of GD5F1GQ5UExxG.
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-4-gch981213@gmail.com
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---
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drivers/mtd/nand/spi/gigadevice.c | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -383,6 +383,16 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ5RExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
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