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QCA808x does not currently fill in the possible_interfaces. This leads to Phylink not being aware that it supports 2500Base-X as well so in cases where it is connected to a DSA switch like MV88E6393 it will limit that port to phy-mode set in the DTS. That means that if SGMII is used you are limited to 1G only while if 2500Base-X was set you are limited to 2.5G only. Populating the possible_interfaces fixes this, so lets backport the patches from kernel 6.9. This also includes a backport of the Phylink PHY validation series from kernel 6.8 that allows the use of possible_interfaces. Link: https://github.com/openwrt/openwrt/pull/15765 Signed-off-by: Robert Marko <robimarko@gmail.com>
45 lines
1.5 KiB
Diff
45 lines
1.5 KiB
Diff
From cb28f702960695e26597c332b0e46776e825cc34 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 28 Feb 2024 18:24:10 +0100
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Subject: [PATCH 2/2] net: phy: qcom: qca808x: fill in possible_interfaces
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Currently QCA808x driver does not fill the possible_interfaces.
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2.5G QCA808x support SGMII and 2500Base-X while 1G model only supports
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SGMII, so fill the possible_interfaces accordingly.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/qcom/qca808x.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/drivers/net/phy/qcom/qca808x.c
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+++ b/drivers/net/phy/qcom/qca808x.c
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@@ -167,6 +167,16 @@ static bool qca808x_is_1g_only(struct ph
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return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
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}
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+static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
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+{
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+ unsigned long *possible = phydev->possible_interfaces;
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+
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+ __set_bit(PHY_INTERFACE_MODE_SGMII, possible);
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+
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+ if (!qca808x_is_1g_only(phydev))
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+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
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+}
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+
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static int qca808x_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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@@ -231,6 +241,8 @@ static int qca808x_config_init(struct ph
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}
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}
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+ qca808x_fill_possible_interfaces(phydev);
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+
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/* Configure adc threshold as 100mv for the link 10M */
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return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
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QCA808X_ADC_THRESHOLD_MASK,
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