openwrt/target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts
Michael Pratt 0976b6c426 ramips: mt7620: use DTS to set PHY base address for external PHYs
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.

`md 0x10117014 1`

PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.

Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.

Also, added a kernel message to display the EPHY base address.

Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.

Signed-off-by: Michael Pratt <mcpratt@pm.me>
2021-06-23 14:22:18 +08:00

199 lines
3.1 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/mtd/partitions/uimage.h>
/ {
compatible = "edimax,ew-7478apc", "ralink,mt7620a-soc";
model = "Edimax EW-7478APC";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
reset_wps {
label = "reset_wps";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "white:power";
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
};
internet {
label = "blue:internet";
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
};
wlan {
label = "blue:wlan";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
usb {
label = "blue:usb";
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
linux,default-trigger = "usbport";
};
};
};
&gpio2 {
status = "okay";
enable_usb_power {
gpio-hog;
line-name = "enable USB power";
gpios = <5 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
label = "cimage";
reg = <0x50000 0x20000>;
read-only;
};
partition@70000 {
compatible = "openwrt,uimage", "denx,uimage";
openwrt,offset = <FW_EDIMAX_OFFSET>;
openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
label = "firmware";
reg = <0x00070000 0x00790000>;
};
};
};
};
&state_default {
gpio {
groups = "i2c", "uartf", "nd_sd";
function = "gpio";
};
};
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
mtd-mac-address = <&factory 0x4>;
mediatek,portmap = "wllll";
port@5 {
status = "okay";
mediatek,fixed-link = <1000 1 1 1>;
phy-mode = "rgmii";
};
mdio-bus {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
};
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "rgmii";
};
phy2: ethernet-phy@2 {
reg = <2>;
phy-mode = "rgmii";
};
phy3: ethernet-phy@3 {
reg = <3>;
phy-mode = "rgmii";
};
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
phy1f: ethernet-phy@1f {
reg = <0x1f>;
phy-mode = "rgmii";
};
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
mediatek,2ghz = <0>;
};
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};