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https://github.com/openwrt/openwrt.git
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ad51e09fd1
Signed-off-by: Felix Fietkau <nbd@nbd.name>
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 061838d68d2c20acb5a57fbd92e3ed0ae906142e Mon Sep 17 00:00:00 2001
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From: Jes Sorensen <Jes.Sorensen@redhat.com>
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Date: Fri, 22 Jul 2016 12:56:30 -0400
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Subject: [PATCH] rtl8xxxu: Initialize GPIO settings for 8188eu
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This matches what the vendor driver does, but is actually opposite of
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what it does for 8192eu.
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Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
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---
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drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 7 +++++++
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drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 1 +
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2 files changed, 8 insertions(+)
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
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@@ -4210,6 +4210,13 @@ static int rtl8xxxu_init_device(struct i
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* Reset USB mode switch setting
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*/
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rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
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+ } else if (priv->rtl_chip == RTL8188E) {
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+ /*
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+ * Init GPIO settings for 8188e
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+ */
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+ val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
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+ val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
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+ rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
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}
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rtl8723a_phy_lc_calibrate(priv);
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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@@ -143,6 +143,7 @@
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#define REG_CAL_TIMER 0x003c
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#define REG_ACLK_MON 0x003e
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#define REG_GPIO_MUXCFG 0x0040
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+#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5)
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#define REG_GPIO_IO_SEL 0x0042
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#define REG_MAC_PINMUX_CFG 0x0043
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#define REG_GPIO_PIN_CTRL 0x0044
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