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https://github.com/openwrt/openwrt.git
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9371542783
This adds support for the Intel Falcon SoC for GPON.
Support for the Falcon SoC was removed in commit c821836395 svn rev:
40392 from OpenWrt, this commit adds it again.
This patch adds a new subtarget for the Falcon SoC, but it still misses
all the drivers needed to control the GPON part.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
389 lines
7.8 KiB
Plaintext
389 lines
7.8 KiB
Plaintext
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,falcon";
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cpus {
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cpu@0 {
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compatible = "mips,mips34kc";
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};
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};
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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};
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clocks {
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compatible = "simple-bus";
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cpu_clk: cpu {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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clock-output-names = "cpu";
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};
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io_clk: io {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "io";
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};
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fpi_clk: fpi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "fpi";
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};
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};
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ebu_cs0: localbus@10000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,localbus", "simple-bus";
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reg = <0x10000000 0x4000000>;
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ranges = <0x0 0x10000000 0x4000000>;
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};
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ebu_cs1: localbus@14000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,localbus", "simple-bus";
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reg = <0x14000000 0x4000000>;
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ranges = <0x0 0x14000000 0x4000000>;
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};
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ebu@18000000 {
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compatible = "lantiq,ebu-falcon";
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reg = <0x18000000 0x100>;
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};
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sbs2@1D000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,sysb2", "simple-bus";
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reg = <0x1D000000 0x1000000>;
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ranges = <0x0 0x1D000000 0x1000000>;
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clock_sysgpe: clock-controller@700000 {
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compatible = "lantiq,sysgpe-falcon";
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reg = <0x700000 0x100>;
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#clock-cells = <1>;
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};
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mps@4000 {
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compatible = "lantiq,mps-falcon", "lantiq,mps-xrx100";
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reg = <0x4000 0x1000>;
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interrupt-parent = <&icu0>;
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interrupts = <154 155>;
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lantiq,mbx = <&mpsmbx>;
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};
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gpio0: gpio@810000 {
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compatible = "lantiq,falcon-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&icu0>;
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interrupts = <44>;
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reg = <0x810000 0x80>;
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clocks = <&clock_syseth 16>;
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};
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gpio2: gpio@810100 {
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compatible = "lantiq,falcon-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&icu0>;
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interrupts = <46>;
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reg = <0x810100 0x80>;
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clocks = <&clock_syseth 17>;
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};
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clock_syseth: clock-controller@B00000 {
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compatible = "lantiq,syseth-falcon";
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reg = <0xB00000 0x100>;
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#clock-cells = <1>;
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};
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pad@B01000 {
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compatible = "lantiq,pad-falcon";
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reg = <0xB01000 0x100>;
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lantiq,bank = <0>;
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clocks = <&clock_syseth 20>;
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};
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pad@B02000 {
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compatible = "lantiq,pad-falcon";
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reg = <0xB02000 0x100>;
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lantiq,bank = <2>;
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clocks = <&clock_syseth 21>;
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};
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};
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fpi@1E000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,fpi", "simple-bus";
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reg = <0x1E000000 0x1000000>;
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ranges = <0x0 0x1E000000 0x1000000>;
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serial1: serial@100B00 {
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status = "disabled";
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compatible = "lantiq,asc";
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reg = <0x100B00 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <112 113 114>;
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line = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&asc1_pins>;
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clocks = <&clock_sys1 11>;
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};
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serial0: serial@100C00 {
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compatible = "lantiq,asc";
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reg = <0x100C00 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <104 105 106>;
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line = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&asc0_pins>;
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clocks = <&clock_sys1 12>;
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};
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spi: spi@100D00 {
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status = "disabled";
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compatible = "intel,falcon-spi", "intel,xrx100-spi", "lantiq,spi-lantiq-ssc";
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interrupts = <22 23 24 25>;
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interrupt-names = "spi_tx", "spi_rx", "spi_err", "spi_frm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x100D00 0x100>;
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interrupt-parent = <&icu0>;
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clocks = <&clock_sys1 13>;
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base_cs = <1>;
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num_cs = <2>;
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};
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gptc@100E00 {
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compatible = "lantiq,gptc-falcon";
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reg = <0x100E00 0x100>;
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};
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i2c: i2c@200000 {
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,lantiq-i2c";
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reg = <0x200000 0x10000>;
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interrupt-parent = <&icu0>;
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interrupts = <18 19 20 21>;
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gpios = <&gpio1 7 0 &gpio1 8 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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clocks = <&clock_sys1 14>;
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};
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gpio1: gpio@800100 {
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compatible = "lantiq,falcon-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&icu0>;
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interrupts = <45>;
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reg = <0x800100 0x100>;
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clocks = <&clock_sys1 16>;
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};
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gpio3: gpio@800200 {
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compatible = "lantiq,falcon-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&icu0>;
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interrupts = <47>;
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reg = <0x800200 0x100>;
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clocks = <&clock_sys1 17>;
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};
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gpio4: gpio@800300 {
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compatible = "lantiq,falcon-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&icu0>;
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interrupts = <48>;
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reg = <0x800300 0x100>;
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clocks = <&clock_sys1 18>;
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};
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pad@800400 {
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compatible = "lantiq,pad-falcon";
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reg = <0x800400 0x100>;
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lantiq,bank = <1>;
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clocks = <&clock_sys1 20>;
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};
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pad@800500 {
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compatible = "lantiq,pad-falcon";
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reg = <0x800500 0x100>;
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lantiq,bank = <3>;
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clocks = <&clock_sys1 21>;
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};
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pad@800600 {
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compatible = "lantiq,pad-falcon";
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reg = <0x800600 0x100>;
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lantiq,bank = <4>;
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clocks = <&clock_sys1 22>;
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};
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status@802000 {
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compatible = "lantiq,status-falcon";
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reg = <0x802000 0x80>;
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};
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clock_sys1: clock-controller@F00000 {
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compatible = "lantiq,sys1-falcon";
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reg = <0xF00000 0x100>;
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#clock-cells = <1>;
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};
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};
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sbs0@1F000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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reg = <0x1F000000 0x400000>;
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ranges = <0x0 0x1F000000 0x400000>;
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mpsmbx: mpsmbx@200000 {
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reg = <0x200000 0x200>;
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};
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};
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sbs1@1F700000 {
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};
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biu@1F800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,biu", "simple-bus";
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reg = <0x1F800000 0x800000>;
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ranges = <0x0 0x1F800000 0x800000>;
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icu0: icu@80200 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "lantiq,icu";
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reg = <0x80200 0x28
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0x80228 0x28
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0x80250 0x28
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0x80278 0x28
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0x802a0 0x28>;
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};
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watchdog@803F0 {
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compatible = "lantiq,wdt";
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reg = <0x803F0 0x10>;
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clocks = <&io_clk>; /* currently no effect */
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};
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};
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pinctrl {
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compatible = "lantiq,pinctrl-falcon";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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/*ntr {
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lantiq,groups = "ntr8k";
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lantiq,function = "ntr";
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};*/
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hrst {
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lantiq,groups = "hrst";
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lantiq,function = "rst";
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};
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};
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asc0_pins: asc0 {
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asc0 {
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lantiq,groups = "asc0";
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lantiq,function = "asc";
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};
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};
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asc1_pins: asc1 {
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asc1 {
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lantiq,groups = "asc1";
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lantiq,function = "asc";
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};
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};
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i2c_pins: i2c {
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i2c {
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lantiq,groups = "i2c";
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lantiq,function = "i2c";
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};
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};
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bootled_pins: bootled {
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bootled {
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lantiq,groups = "bootled";
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lantiq,function = "led";
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};
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};
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ntr_ntr8k: ntr8k {
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ntr8k {
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lantiq,groups = "ntr8k";
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lantiq,function = "ntr";
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};
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};
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ntr_pps: pps {
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pps {
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lantiq,groups = "pps";
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lantiq,function = "ntr";
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};
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};
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ntr_gpio: gpio {
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gpio {
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lantiq,pins = "io5";
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lantiq,mux = <1>;
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lantiq,output = <0>;
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};
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};
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slic_pins: slic {
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slic {
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lantiq,groups = "slic";
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lantiq,function = "slic";
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};
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};
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};
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pinselect-ntr {
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compatible = "lantiq,onu-ntr","lantiq,pinselect-ntr";
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pinctrl-names = "ntr8k", "pps", "gpio";
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pinctrl-0 = <&ntr_ntr8k>;
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pinctrl-1 = <&ntr_pps>;
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pinctrl-2 = <&ntr_gpio>;
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};
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pinselect-asc1 {
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compatible = "lantiq,onu-asc1","lantiq,pinselect-asc1";
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pinctrl-names = "default", "asc1";
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pinctrl-0 = <&slic_pins>;
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pinctrl-1 = <&asc1_pins>;
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};
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};
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