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61 lines
2.3 KiB
Diff
61 lines
2.3 KiB
Diff
From 6f421cda8e6e43f74b8f8a7f63db67c6d3ac9ba3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 11 Apr 2012 18:43:50 +0200
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Subject: [PATCH 67/70] MIPS: lantiq: fix dwc_otg usb for ase
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changed irq number and pmu settings. little bit of fiddling to get the now variable
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irq into resources.
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Signed-off-by: Conor O'Gorman <i@conorogorman.net>
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 1 +
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drivers/usb/dwc_otg/dwc_otg_driver.c | 3 +++
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drivers/usb/dwc_otg/dwc_otg_ifx.c | 5 ++++-
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3 files changed, 8 insertions(+), 1 deletions(-)
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diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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index b7f10e6..d9c892b 100644
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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@@ -36,6 +36,7 @@
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#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
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#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
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+#define LTQ_USB_ASE_INT (INT_NUM_IM0_IRL0 + 31)
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#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
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#define MIPS_CPU_TIMER_IRQ 7
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diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.c b/drivers/usb/dwc_otg/dwc_otg_driver.c
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index 1b0daab..5c64ebb 100644
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--- a/drivers/usb/dwc_otg/dwc_otg_driver.c
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+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
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@@ -860,6 +860,9 @@ static int __init dwc_otg_init(void)
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printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
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+ if (ltq_is_ase())
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+ dwc_irq = LTQ_USB_ASE_INT;
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+
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// ifxmips setup
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retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
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if (retval < 0)
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diff --git a/drivers/usb/dwc_otg/dwc_otg_ifx.c b/drivers/usb/dwc_otg/dwc_otg_ifx.c
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index 0a4c209..e45da85 100644
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--- a/drivers/usb/dwc_otg/dwc_otg_ifx.c
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+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
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@@ -61,7 +61,10 @@ void dwc_otg_power_on (void)
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// clear power
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writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
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// set clock gating
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- writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
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+ if (ltq_is_ase())
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+ writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
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+ else
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+ writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
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// set power
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writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
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writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);
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--
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1.7.9.1
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