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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
60 lines
1.5 KiB
Diff
60 lines
1.5 KiB
Diff
From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 31 Dec 2021 17:56:14 +0100
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Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
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Now that CPU clock is exposed and can be controlled, add the necessary
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properties to the CPU nodes.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -5,6 +5,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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+#include <dt-bindings/clock/qcom,apss-ipq.h>
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/ {
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#address-cells = <2>;
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@@ -38,6 +39,8 @@
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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CPU1: cpu@1 {
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@@ -46,6 +49,8 @@
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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CPU2: cpu@2 {
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@@ -54,6 +59,8 @@
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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CPU3: cpu@3 {
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@@ -62,6 +69,8 @@
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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L2_0: l2-cache {
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