mirror of
https://github.com/openwrt/openwrt.git
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95ebd609ae
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.139
Removed upstreamed:
x86/patches-5.15/120-hwrng-geode-fix-accessing-registers.patch[3]
All other patches automatically rebased.
3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.139&id=a5c83c8043d70b9a28d1bd78a2dbbab340f43889
Build system: x86_64
Build-tested: ramips/tplink_archer-a6-v3
Run-tested: ramips/tplink_archer-a6-v3
Signed-off-by: John Audia <therealgraysky@proton.me>
[Refresh on top of OpenWrt 23.05]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit df167450a5)
52 lines
1.8 KiB
Diff
52 lines
1.8 KiB
Diff
From f7fb35d540240889a8f45f3fd42363cbc1a448e2 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Fri, 19 Aug 2022 00:06:20 +0200
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Subject: [PATCH] clk: qcom: clk-rcg2: add rcg2 mux ops
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An RCG may act as a mux that switch between 2 parents.
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This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
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the CPU cluster clock just switches between XO and the PLL that feeds it.
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Add the required ops to add support for this special configuration and use
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the generic mux function to determine the rate.
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This way we dont have to keep a essentially dummy frequency table to use
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RCG2 as a mux.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
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---
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drivers/clk/qcom/clk-rcg.h | 1 +
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drivers/clk/qcom/clk-rcg2.c | 7 +++++++
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2 files changed, 8 insertions(+)
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--- a/drivers/clk/qcom/clk-rcg.h
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+++ b/drivers/clk/qcom/clk-rcg.h
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@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
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extern const struct clk_ops clk_rcg2_ops;
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extern const struct clk_ops clk_rcg2_floor_ops;
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+extern const struct clk_ops clk_rcg2_mux_closest_ops;
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extern const struct clk_ops clk_edp_pixel_ops;
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extern const struct clk_ops clk_byte_ops;
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extern const struct clk_ops clk_byte2_ops;
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--- a/drivers/clk/qcom/clk-rcg2.c
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+++ b/drivers/clk/qcom/clk-rcg2.c
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@@ -471,6 +471,13 @@ const struct clk_ops clk_rcg2_floor_ops
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
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+const struct clk_ops clk_rcg2_mux_closest_ops = {
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+ .determine_rate = __clk_mux_determine_rate_closest,
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+ .get_parent = clk_rcg2_get_parent,
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+ .set_parent = clk_rcg2_set_parent,
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+};
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+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
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+
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struct frac_entry {
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int num;
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int den;
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