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6876465875
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.
`md 0x10117014 1`
PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.
Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.
Also, added a kernel message to display the EPHY base address.
Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 0976b6c426)
175 lines
2.7 KiB
Plaintext
175 lines
2.7 KiB
Plaintext
#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "zyxel,keenetic-viva", "ralink,mt7620a-soc";
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model = "ZyXEL Keenetic Viva";
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aliases {
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led-boot = &led_power_green;
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led-failsafe = &led_power_green;
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led-running = &led_power_green;
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led-upgrade = &led_power_green;
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};
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leds {
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compatible = "gpio-leds";
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wan {
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label = "green:wan";
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gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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};
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usb {
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label = "green:usb";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ohci_port1>, <&ehci_port1>;
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linux,default-trigger = "usbport";
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};
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power_alert {
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label = "red:power";
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gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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};
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wifi {
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label = "green:wifi";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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};
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led_power_green: power {
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label = "green:power";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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fn {
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label = "fn";
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gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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usb_power {
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gpio-export,name = "usb";
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gpio-export,output = <1>;
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gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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};
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};
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rtl8367rb {
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compatible = "realtek,rtl8367b";
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cpu_port = <7>;
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realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
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mii-bus = <&mdio0>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0xfb0000>;
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};
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "uartf";
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function = "gpio";
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii2_pins &mdio_pins>;
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mtd-mac-address = <&factory 0x4>;
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port@4 {
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status = "okay";
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mediatek,fixed-link = <1000 1 1 1>;
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phy-mode = "rgmii";
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phy-handle = <&phy4>;
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};
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mdio0: mdio-bus {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,port4-gmac;
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mediatek,ephy-base = /bits/ 8 <8>;
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0x0>;
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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