mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 08:51:13 +00:00
64f4c3ef35
The board is manufactured by Digilent Main features: - Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20) - RAM: 1 GB DDR3L - FLASH: 16 MB QSPI - 1 Gbps Ethernet - USB 2.0 - microSD slot - Pcam camera connector - HDMI Tx and Rx - Audio codec: stereo out, stereo in, mic - 5 (Z7-10) or 6 (Z7-20) Pmod ports - 6 push-buttons, 4 switches, 5 LEDs - 1 (Z7-10) or 2 (Z7-20) RGB LEDs Signed-off-by: Luis Araneda <luaraneda@gmail.com>
95 lines
2.1 KiB
Diff
95 lines
2.1 KiB
Diff
From ba5c7a032c2ae66d5467820daab898e5f9048405 Mon Sep 17 00:00:00 2001
|
|
From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu@cybertrust.co.jp>
|
|
Date: Wed, 28 Feb 2018 11:25:52 +0900
|
|
Subject: [PATCH] arm: dts: zynq: Add Digilent Zybo Z7 board
|
|
|
|
This add a DTS for the Digilent Zybo Z7 board.
|
|
This board is the successor board of Zybo, these are almost the same except
|
|
for ps-clk-frequency specifications.
|
|
|
|
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu@cybertrust.co.jp>
|
|
Reviewed-by: Rob Herring <robh@kernel.org>
|
|
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
---
|
|
Modifications:
|
|
- Removed changes to file Documentation/devicetree/bindings/arm/xilinx.txt
|
|
---
|
|
arch/arm/boot/dts/Makefile | 3 +-
|
|
arch/arm/boot/dts/zynq-zybo-z7.dts | 58 +++++++++++++++++++
|
|
2 files changed, 60 insertions(+), 1 deletion(-)
|
|
create mode 100644 arch/arm/boot/dts/zynq-zybo-z7.dts
|
|
|
|
--- a/arch/arm/boot/dts/Makefile
|
|
+++ b/arch/arm/boot/dts/Makefile
|
|
@@ -1006,7 +1006,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
|
|
zynq-zc702.dtb \
|
|
zynq-zc706.dtb \
|
|
zynq-zed.dtb \
|
|
- zynq-zybo.dtb
|
|
+ zynq-zybo.dtb \
|
|
+ zynq-zybo-z7.dtb
|
|
dtb-$(CONFIG_MACH_ARMADA_370) += \
|
|
armada-370-db.dtb \
|
|
armada-370-dlink-dns327l.dtb \
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/zynq-zybo-z7.dts
|
|
@@ -0,0 +1,58 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+
|
|
+/dts-v1/;
|
|
+#include "zynq-7000.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Zynq ZYBO Z7 Development Board";
|
|
+ compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = &gem0;
|
|
+ serial0 = &uart1;
|
|
+ };
|
|
+
|
|
+ memory@0 {
|
|
+ device_type = "memory";
|
|
+ reg = <0x0 0x20000000>;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ bootargs = "";
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ usb_phy0: phy0 {
|
|
+ #phy-cells = <0>;
|
|
+ compatible = "usb-nop-xceiv";
|
|
+ reset-gpios = <&gpio0 46 1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&clkc {
|
|
+ ps-clk-frequency = <33333333>;
|
|
+};
|
|
+
|
|
+&gem0 {
|
|
+ status = "okay";
|
|
+ phy-mode = "rgmii-id";
|
|
+ phy-handle = <ðernet_phy>;
|
|
+
|
|
+ ethernet_phy: ethernet-phy@0 {
|
|
+ reg = <0>;
|
|
+ device_type = "ethernet-phy";
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdhci0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb0 {
|
|
+ status = "okay";
|
|
+ dr_mode = "host";
|
|
+ usb-phy = <&usb_phy0>;
|
|
+};
|