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https://github.com/openwrt/openwrt.git
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74a8f416f4
Rebase local patches on top of quarterly timed release, allowing to drop numerous patches which have been accepted upstream since the release of U-Boot 2023.07.02. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
550 lines
18 KiB
Diff
550 lines
18 KiB
Diff
From 8d0665327819c41fce2c8d50f19c967b22eae564 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 27 Jul 2022 16:36:13 +0800
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Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel
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Backport new features from upstream kernel
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/mtd/nand/spi/Kconfig | 1 +
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drivers/mtd/nand/spi/Makefile | 2 +-
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drivers/mtd/nand/spi/core.c | 102 ++++++----
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drivers/mtd/nand/spi/etron.c | 181 +++++++++++++++++
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drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++----
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drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++---
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drivers/mtd/nand/spi/micron.c | 50 ++---
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drivers/mtd/nand/spi/toshiba.c | 66 +++---
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drivers/mtd/nand/spi/winbond.c | 164 ++++++++++++---
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include/linux/mtd/spinand.h | 87 +++++---
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10 files changed, 923 insertions(+), 225 deletions(-)
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create mode 100644 drivers/mtd/nand/spi/etron.c
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--- a/drivers/mtd/nand/spi/Makefile
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+++ b/drivers/mtd/nand/spi/Makefile
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@@ -1,4 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
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+spinand-objs := core.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
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obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
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--- a/drivers/mtd/nand/spi/core.c
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+++ b/drivers/mtd/nand/spi/core.c
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@@ -822,6 +822,7 @@ static const struct nand_ops spinand_ops
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};
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static const struct spinand_manufacturer *spinand_manufacturers[] = {
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+ &etron_spinand_manufacturer,
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&gigadevice_spinand_manufacturer,
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¯onix_spinand_manufacturer,
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µn_spinand_manufacturer,
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--- /dev/null
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+++ b/drivers/mtd/nand/spi/etron.c
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@@ -0,0 +1,181 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2020 Etron Technology, Inc.
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+ *
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+ */
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+#ifndef __UBOOT__
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+#include <malloc.h>
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+#include <linux/device.h>
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+#include <linux/kernel.h>
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+#endif
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+#include <linux/bug.h>
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+#include <linux/mtd/spinand.h>
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+
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+#define SPINAND_MFR_ETRON 0xD5
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+
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+#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
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+
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+static SPINAND_OP_VARIANTS(read_cache_variants,
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+
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+static SPINAND_OP_VARIANTS(write_cache_variants,
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+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
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+
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+static SPINAND_OP_VARIANTS(update_cache_variants,
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+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
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+
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+static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section > 3)
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+ return -ERANGE;
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+
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+ region->offset = (14 * section) + 72;
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+ region->length = 14;
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+
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+ return 0;
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+}
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+
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+static int etron_ooblayout_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section > 3)
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+ return -ERANGE;
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+
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+ if (section) {
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+ region->offset = 18 * section;
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+ region->length = 18;
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+ } else {
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+ /* section 0 has one byte reserved for bad block mark */
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+ region->offset = 2;
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+ region->length = 16;
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+ }
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+ return 0;
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+}
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+
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+static const struct mtd_ooblayout_ops etron_ooblayout = {
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+ .ecc = etron_ooblayout_ecc,
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+ .rfree = etron_ooblayout_free,
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+};
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+
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+static int etron_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ struct nand_device *nand = spinand_to_nand(spinand);
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+
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+ switch (status & STATUS_ECC_MASK) {
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+ case STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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+
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+ case STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ case STATUS_ECC_HAS_BITFLIPS:
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+ return nand->eccreq.strength >> 1;
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+
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+ case STATUS_ECC_LIMIT_BITFLIPS:
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+ return nand->eccreq.strength;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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+static const struct spinand_info etron_spinand_table[] = {
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+ /* EM73C 1Gb 3.3V */
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+ SPINAND_INFO("EM73C044VCF",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
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+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+ /* EM7xD 2Gb */
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+ SPINAND_INFO("EM73D044VCR",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
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+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+ SPINAND_INFO("EM73D044VCO",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+ SPINAND_INFO("EM78D044VCM",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+ /* EM7xE 4Gb */
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+ SPINAND_INFO("EM73E044VCE",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
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+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+ SPINAND_INFO("EM78E044VCD",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
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+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+ /* EM7xF044VCA 8Gb */
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+ SPINAND_INFO("EM73F044VCA",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
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+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+ SPINAND_INFO("EM78F044VCA",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
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+ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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+};
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+
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+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
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+};
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+
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+const struct spinand_manufacturer etron_spinand_manufacturer = {
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+ .id = SPINAND_MFR_ETRON,
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+ .name = "Etron",
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+ .chips = etron_spinand_table,
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+ .nchips = ARRAY_SIZE(etron_spinand_table),
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+ .ops = &etron_spinand_manuf_ops,
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+};
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va
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SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
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+/* Q5 1Gb */
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+static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+
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+/* Q5 2Gb & 4Gb */
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+static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
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return -EINVAL;
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}
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+static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section > 3)
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+ return -ERANGE;
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+
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+ region->offset = (16 * section) + 8;
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+ region->length = 8;
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+
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+ return 0;
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+}
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+
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+static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section > 3)
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+ return -ERANGE;
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+
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+ region->offset = (16 * section) + 2;
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+ region->length = 6;
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+
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+ return 0;
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+}
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+
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+static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
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+ .ecc = esmt_1_ooblayout_ecc,
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+ .rfree = esmt_1_ooblayout_free,
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+ };
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+
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static const struct spinand_info gigadevice_spinand_table[] = {
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+ SPINAND_INFO("F50L1G41LB",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
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+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
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SPINAND_INFO("GD5F1GQ4xA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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@@ -349,6 +405,87 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GQ5UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ6UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
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+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GM7UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GM7UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GM8UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
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+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ5UExxH",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
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+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GQ5UExxH",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
|
|
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ SPINAND_HAS_QE_BIT,
|
|
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
|
+ gd5fxgq5xexxg_ecc_get_status)),
|
|
+ SPINAND_INFO("GD5F4GQ6UExxH",
|
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
|
|
+ NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ SPINAND_HAS_QE_BIT,
|
|
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
|
+ gd5fxgq5xexxg_ecc_get_status)),
|
|
+
|
|
};
|
|
|
|
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
|
|
--- a/drivers/mtd/nand/spi/winbond.c
|
|
+++ b/drivers/mtd/nand/spi/winbond.c
|
|
@@ -18,6 +18,23 @@
|
|
|
|
#define WINBOND_CFG_BUF_READ BIT(3)
|
|
|
|
+#define W25N02_N04KV_STATUS_ECC_MASK (3 << 4)
|
|
+#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
|
|
+#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS (1 << 4)
|
|
+#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
|
|
+#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
|
|
+
|
|
+#define W25N01_M02GV_STATUS_ECC_MASK (3 << 4)
|
|
+#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS (0 << 4)
|
|
+#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4)
|
|
+#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4)
|
|
+
|
|
+#define W25N01KV_STATUS_ECC_MASK (3 << 4)
|
|
+#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
|
|
+#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4)
|
|
+#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4)
|
|
+#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
|
|
+
|
|
static SPINAND_OP_VARIANTS(read_cache_variants,
|
|
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
|
|
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
|
|
@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_
|
|
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
|
|
SPINAND_PROG_LOAD(false, 0, NULL, 0));
|
|
|
|
+static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section,
|
|
+ struct mtd_oob_region *region)
|
|
+{
|
|
+ if (section > 3)
|
|
+ return -ERANGE;
|
|
+
|
|
+ region->offset = (16 * section) + 64;
|
|
+ region->length = 16;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section,
|
|
+ struct mtd_oob_region *region)
|
|
+{
|
|
+ if (section > 3)
|
|
+ return -ERANGE;
|
|
+
|
|
+ region->offset = (16 * section) + 2;
|
|
+ region->length = 14;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = {
|
|
+ .ecc = w25n02kv_n04kv_ooblayout_ecc,
|
|
+ .rfree = w25n02kv_n04kv_ooblayout_free,
|
|
+};
|
|
+
|
|
static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
|
|
struct mtd_oob_region *region)
|
|
{
|
|
@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2
|
|
.rfree = w25n02kv_ooblayout_free,
|
|
};
|
|
|
|
+static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
|
|
+ u8 status)
|
|
+{
|
|
+ switch (status & W25N01KV_STATUS_ECC_MASK) {
|
|
+ case W25N01KV_STATUS_ECC_NO_BITFLIPS:
|
|
+ return 0;
|
|
+
|
|
+ case W25N01KV_STATUS_ECC_1_3_BITFLIPS:
|
|
+ return 3;
|
|
+
|
|
+ case W25N01KV_STATUS_ECC_4_BITFLIPS:
|
|
+ return 4;
|
|
+
|
|
+ case W25N01KV_STATUS_ECC_UNCOR_ERROR:
|
|
+ return -EBADMSG;
|
|
+
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ return -EINVAL;
|
|
+}
|
|
+
|
|
+static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
|
|
+ u8 status)
|
|
+{
|
|
+ switch (status & W25N02_N04KV_STATUS_ECC_MASK) {
|
|
+ case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS:
|
|
+ return 0;
|
|
+
|
|
+ case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS:
|
|
+ return 3;
|
|
+
|
|
+ case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS:
|
|
+ return 4;
|
|
+
|
|
+ /* W25N02_N04KV_use internal 8bit ECC algorithm.
|
|
+ * But the ECC strength is 4 bit requried.
|
|
+ * Return 3 if the bit bit flip count less than 5.
|
|
+ * Return 4 if the bit bit flip count more than 5 to 8.
|
|
+ */
|
|
+
|
|
+ case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR:
|
|
+ return -EBADMSG;
|
|
+
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ return -EINVAL;
|
|
+}
|
|
+
|
|
static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
|
|
u8 status)
|
|
{
|
|
@@ -163,6 +261,15 @@ static const struct spinand_info winbond
|
|
&update_cache_variants),
|
|
0,
|
|
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
|
|
+ SPINAND_INFO("W25N01KV",
|
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
|
|
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ 0,
|
|
+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
|
|
SPINAND_INFO("W25N02KV",
|
|
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
|
|
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
|
|
@@ -172,6 +279,16 @@ static const struct spinand_info winbond
|
|
&update_cache_variants),
|
|
0,
|
|
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
|
|
+ SPINAND_INFO("W25N04KV",
|
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
|
|
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ 0,
|
|
+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
|
|
+ w25n02kv_n04kv_ecc_get_status)),
|
|
};
|
|
|
|
static int winbond_spinand_init(struct spinand_device *spinand)
|
|
--- a/include/linux/mtd/spinand.h
|
|
+++ b/include/linux/mtd/spinand.h
|
|
@@ -245,6 +245,7 @@ struct spinand_manufacturer {
|
|
};
|
|
|
|
/* SPI NAND manufacturers */
|
|
+extern const struct spinand_manufacturer etron_spinand_manufacturer;
|
|
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
|
|
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
|
|
extern const struct spinand_manufacturer micron_spinand_manufacturer;
|