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eca8a2ee0d
Refreshed all patches. Fixes: - CVE-2019-14896 - CVE-2019-14897 Remove upstreamed: - 023-0007-crypto-crypto4xx-Fix-wrong-ppc4xx_trng_probe-ppc4xx_.patch - 001-4.22-01-MIPS-BCM63XX-drop-unused-and-broken-DSP-platform-dev.patch Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
127 lines
3.9 KiB
Diff
127 lines
3.9 KiB
Diff
From 68502f802a66b68a6b5fefb52e709807a702a94b Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Mon, 26 Nov 2018 19:46:58 +0000
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Subject: [PATCH 443/454] net: lan78xx: Support auto-downshift to 100Mb/s
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Ethernet cables with faulty or missing pairs (specifically pairs C and
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D) allow auto-negotiation to 1000Mbs, but do not support the successful
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establishment of a link. Add a DT property, "microchip,downshift-after",
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to configure the number of auto-negotiation failures after which it
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falls back to 100Mbs. Valid values are 2, 3, 4, 5 and 0, where 0 means
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never downshift.
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/net/phy/microchip.c | 33 +++++++++++++++++++++++++++++++++
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drivers/net/usb/lan78xx.c | 8 ++++++--
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include/linux/microchipphy.h | 11 +++++++++++
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3 files changed, 50 insertions(+), 2 deletions(-)
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--- a/drivers/net/phy/microchip.c
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+++ b/drivers/net/phy/microchip.c
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@@ -21,6 +21,7 @@
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#include <linux/phy.h>
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#include <linux/microchipphy.h>
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#include <linux/delay.h>
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+#include <linux/of.h>
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#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
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#define DRIVER_DESC "Microchip LAN88XX PHY driver"
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@@ -225,6 +226,7 @@ static int lan88xx_probe(struct phy_devi
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{
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struct device *dev = &phydev->mdio.dev;
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struct lan88xx_priv *priv;
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+ u32 downshift_after = 0;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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@@ -232,6 +234,37 @@ static int lan88xx_probe(struct phy_devi
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priv->wolopts = 0;
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+ if (!of_property_read_u32(dev->of_node,
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+ "microchip,downshift-after",
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+ &downshift_after)) {
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+ u32 mask = LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK;
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+ u32 val = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
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+
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+ switch (downshift_after) {
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+ case 2:
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+ val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2;
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+ break;
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+ case 3:
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+ val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3;
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+ break;
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+ case 4:
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+ val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4;
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+ break;
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+ case 5:
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+ val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5;
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+ break;
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+ case 0:
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+ /* Disable completely */
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+ mask = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
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+ val = 0;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+ (void)phy_modify_paged(phydev, 1, LAN78XX_PHY_CTRL3,
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+ mask, val);
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+ }
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+
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/* these values can be used to identify internal PHY */
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priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
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priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
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--- a/drivers/net/usb/lan78xx.c
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+++ b/drivers/net/usb/lan78xx.c
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@@ -37,7 +37,8 @@
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/microchipphy.h>
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-#include <linux/phy.h>
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+#include <linux/phy_fixed.h>
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+#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include "lan78xx.h"
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@@ -1764,6 +1765,7 @@ done:
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static int lan78xx_mdio_init(struct lan78xx_net *dev)
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{
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+ struct device_node *node;
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int ret;
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dev->mdiobus = mdiobus_alloc();
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@@ -1793,7 +1795,9 @@ static int lan78xx_mdio_init(struct lan7
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break;
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}
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- ret = mdiobus_register(dev->mdiobus);
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+ node = of_get_child_by_name(dev->udev->dev.of_node, "mdio");
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+ ret = of_mdiobus_register(dev->mdiobus, node);
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+ of_node_put(node);
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if (ret) {
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netdev_err(dev->net, "can't register MDIO bus\n");
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goto exit1;
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--- a/include/linux/microchipphy.h
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+++ b/include/linux/microchipphy.h
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@@ -70,6 +70,17 @@
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#define LAN88XX_MMD3_CHIP_ID (32877)
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#define LAN88XX_MMD3_CHIP_REV (32878)
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+/* Registers specific to the LAN7800/LAN7850 embedded phy */
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+#define LAN78XX_PHY_LED_MODE_SELECT (0x1D)
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+
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+#define LAN78XX_PHY_CTRL3 (0x14)
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+#define LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT (0x0010)
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+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK (0x000c)
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+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2 (0x0000)
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+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3 (0x0004)
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+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4 (0x0008)
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+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5 (0x000c)
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+
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/* DSP registers */
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#define PHY_ARDENNES_MMD_DEV_3_PHY_CFG (0x806A)
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#define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_ (0x2000)
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