openwrt/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
Michael Lyle 961e01fc67 ramips: gl-mt1300: downclock SPI to 50MHz
The SPI max frequency was set to 80MHz, considerably higher than the
vendor clocks it in their firmware (10MHz).  Multiple users reported
jffs2 corruption/instability in GitHub issue #10461.

My unit has a W25Q256; datasheet specifies maximum SPI frequency for
read command of 50MHz.

Thanks to @DragonBlueP for suggesting to eliminate m25p,fast-read;
and @MPannen1979 for identifying the problem.

Fixes: #10461
Signed-off-by: Michael Lyle <mlyle@lyle.org>
2022-11-07 12:54:31 +01:00

172 lines
2.5 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "glinet,gl-mt1300", "mediatek,mt7621-soc";
model = "GL.iNet GL-MT1300";
aliases {
led-boot = &led_run;
led-failsafe = &led_run;
led-running = &led_run;
led-upgrade = &led_run;
label-mac-device = &gmac1;
};
chosen {
bootargs = "console=ttyS0,115200";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
switch {
label = "switch";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
};
leds {
compatible = "gpio-leds";
led_run: run {
label = "blue:run";
gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
};
system {
label = "white:system";
gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
};
};
};
&i2c {
status = "okay";
};
&sdhci {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
broken-flash-reset;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x1fb0000>;
};
};
};
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x0>;
};
};
&gmac0 {
nvmem-cells = <&macaddr_factory_4000>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&gmac1 {
status = "okay";
label = "wan";
phy-handle = <&ethphy4>;
nvmem-cells = <&macaddr_factory_4000>;
nvmem-cell-names = "mac-address";
};
&mdio {
ethphy4: ethernet-phy@4 {
reg = <4>;
};
};
&switch0 {
ports {
port@2 {
status = "okay";
label = "lan1";
};
port@3 {
status = "okay";
label = "lan2";
};
};
};
&uartlite3 {
status = "okay";
};
&state_default {
gpio {
group = "wdt", "jtag";
function = "gpio";
};
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4000: macaddr@4000 {
reg = <0x4000 0x6>;
};
};