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0dcbe4e931
Copy config and patches from 5.15. This simplifies reviewing process. Signed-off-by: Nick Hainke <vincent@systemli.org>
146 lines
4.5 KiB
Diff
146 lines
4.5 KiB
Diff
From daf73c70f69386fb15960526772ef584a4efcaf2 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 19 Jun 2023 06:09:36 +0200
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Subject: [PATCH 4/9] mips: ralink: rt305x: remove clock related code
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A properly clock driver for ralink SoCs has been added. Hence there is no
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need to have clock related code in 'arch/mips/ralink' folder anymore.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/include/asm/mach-ralink/rt305x.h | 21 --------
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arch/mips/ralink/rt305x.c | 78 ------------------------------
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2 files changed, 99 deletions(-)
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--- a/arch/mips/include/asm/mach-ralink/rt305x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -66,26 +66,9 @@ static inline int soc_is_rt5350(void)
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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-#define RT305X_SYSCFG_CPUCLK_SHIFT 18
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-#define RT305X_SYSCFG_CPUCLK_MASK 0x1
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-#define RT305X_SYSCFG_CPUCLK_LOW 0x0
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-#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
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-
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#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
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-#define RT305X_SYSCFG_CPUCLK_MASK 0x1
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#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
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-#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
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-#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
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-#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
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-#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
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-
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-#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
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-#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
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-#define RT5350_SYSCFG0_CPUCLK_360 0x0
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-#define RT5350_SYSCFG0_CPUCLK_320 0x2
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-#define RT5350_SYSCFG0_CPUCLK_300 0x3
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-
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#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
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#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
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#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
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@@ -116,13 +99,9 @@ static inline int soc_is_rt5350(void)
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#define RT3352_SYSC_REG_SYSCFG0 0x010
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#define RT3352_SYSC_REG_SYSCFG1 0x014
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-#define RT3352_SYSC_REG_CLKCFG1 0x030
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#define RT3352_SYSC_REG_RSTCTRL 0x034
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#define RT3352_SYSC_REG_USB_PS 0x05c
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-#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
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-#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
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-#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
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#define RT3352_RSTCTRL_UHST BIT(22)
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#define RT3352_RSTCTRL_UDEV BIT(25)
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#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -53,84 +53,6 @@ static unsigned long rt5350_get_mem_size
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return ret;
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}
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-void __init ralink_clk_init(void)
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-{
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- unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
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- unsigned long wmac_rate = 40000000;
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-
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- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
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-
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- if (soc_is_rt305x() || soc_is_rt3350()) {
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- t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
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- RT305X_SYSCFG_CPUCLK_MASK;
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- switch (t) {
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- case RT305X_SYSCFG_CPUCLK_LOW:
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- cpu_rate = 320000000;
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- break;
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- case RT305X_SYSCFG_CPUCLK_HIGH:
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- cpu_rate = 384000000;
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- break;
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- }
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- sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
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- } else if (soc_is_rt3352()) {
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- t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
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- RT3352_SYSCFG0_CPUCLK_MASK;
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- switch (t) {
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- case RT3352_SYSCFG0_CPUCLK_LOW:
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- cpu_rate = 384000000;
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- break;
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- case RT3352_SYSCFG0_CPUCLK_HIGH:
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- cpu_rate = 400000000;
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- break;
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- }
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- sys_rate = wdt_rate = cpu_rate / 3;
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- uart_rate = 40000000;
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- } else if (soc_is_rt5350()) {
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- t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
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- RT5350_SYSCFG0_CPUCLK_MASK;
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- switch (t) {
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- case RT5350_SYSCFG0_CPUCLK_360:
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- cpu_rate = 360000000;
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- sys_rate = cpu_rate / 3;
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- break;
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- case RT5350_SYSCFG0_CPUCLK_320:
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- cpu_rate = 320000000;
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- sys_rate = cpu_rate / 4;
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- break;
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- case RT5350_SYSCFG0_CPUCLK_300:
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- cpu_rate = 300000000;
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- sys_rate = cpu_rate / 3;
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- break;
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- default:
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- BUG();
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- }
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- uart_rate = 40000000;
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- wdt_rate = sys_rate;
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- } else {
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- BUG();
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- }
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-
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- if (soc_is_rt3352() || soc_is_rt5350()) {
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- u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
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-
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- if (!(val & RT3352_CLKCFG0_XTAL_SEL))
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- wmac_rate = 20000000;
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- }
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-
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- ralink_clk_add("cpu", cpu_rate);
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- ralink_clk_add("sys", sys_rate);
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- ralink_clk_add("10000900.i2c", uart_rate);
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- ralink_clk_add("10000a00.i2s", uart_rate);
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- ralink_clk_add("10000b00.spi", sys_rate);
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- ralink_clk_add("10000b40.spi", sys_rate);
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- ralink_clk_add("10000100.timer", wdt_rate);
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- ralink_clk_add("10000120.watchdog", wdt_rate);
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- ralink_clk_add("10000500.uart", uart_rate);
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- ralink_clk_add("10000c00.uartlite", uart_rate);
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- ralink_clk_add("10100000.ethernet", sys_rate);
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- ralink_clk_add("10180000.wmac", wmac_rate);
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-}
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-
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
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