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eb69d7a4ff
Refresh kernel patches for version 6.1. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
96 lines
2.7 KiB
Diff
96 lines
2.7 KiB
Diff
From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Mon, 17 Jan 2022 23:39:34 +0100
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Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
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ipq8064
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Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
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Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
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for the secondary mux.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Tested-by: Jonathan McDowell <noodles@earth.li>
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---
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
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1 file changed, 32 insertions(+), 2 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -301,6 +301,12 @@
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};
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clocks {
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+ qsb: qsb {
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+ compatible = "fixed-clock";
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+ clock-frequency = <225000000>;
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+ #clock-cells = <0>;
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+ };
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+
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cxo_board: cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -490,6 +490,17 @@
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clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
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clock-names = "pll8_vote", "pxo";
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clock-output-names = "acpu_l2_aux";
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+ #clock-cells = <0>;
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+ };
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+
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+ kraitcc: clock-controller {
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+ compatible = "qcom,krait-cc-v1";
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+ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
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+ <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
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+ clock-names = "hfpll0", "hfpll1", "hfpll_l2",
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+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
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+ "qsb", "pxo";
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+ #clock-cells = <1>;
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};
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acc0: clock-controller@2088000 {
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@@ -503,17 +509,25 @@
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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+ clock-output-names = "acpu0_aux";
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+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
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+ clock-names = "pll8_vote", "pxo";
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+ #clock-cells = <0>;
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};
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saw0: regulator@2089000 {
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- compatible = "qcom,saw2";
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+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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+ clock-output-names = "acpu1_aux";
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+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
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+ clock-names = "pll8_vote", "pxo";
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+ #clock-cells = <0>;
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};
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saw1: regulator@2099000 {
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@@ -531,11 +545,17 @@
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};
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saw1: regulator@2099000 {
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- compatible = "qcom,saw2";
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+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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+ saw_l2: regulator@02012000 {
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+ compatible = "qcom,saw2", "syscon";
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+ reg = <0x02012000 0x1000>;
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+ regulator;
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+ };
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+
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nss_common: syscon@03000000 {
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compatible = "syscon";
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reg = <0x03000000 0x0000FFFF>;
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