openwrt/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts
Jan Forman 328546e108 ath79: increase max SPI clock for DIR-859 A1
Increase the spi-max frequency to 50 MHz, similar to the DIR-842.

Signed-off-by: Jan Forman <forman.jan96@gmail.com>
[improve commit title, fix commit message alignment]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-04-10 20:57:37 +02:00

164 lines
2.7 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca956x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "D-Link DIR-859 A1";
compatible = "dlink,dir-859-a1", "qca,qca9563";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
leds {
compatible = "gpio-leds";
wps {
label = "green:wps";
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
};
led_power: power {
label = "green:power";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
internet {
label = "green:internet";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
wlan {
label = "green:wlan";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
keys {
compatible = "gpio-keys";
wps {
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
reset {
linux,code = <KEY_RESTART>;
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
gpio-export {
compatible = "gpio-export";
#size-cells = <0>;
gpio_switch_reset {
gpio-export,name = "dir-859-a1:reset:switch";
gpio-export,output = <1>;
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
};
};
};
&pcie {
status = "okay";
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x000000 0x40000>;
read-only;
};
partition@40000 {
label = "bdcfg";
reg = <0x040000 0x10000>;
read-only;
};
partition@50000 {
label = "devdata";
reg = <0x050000 0x10000>;
read-only;
};
partition@60000 {
label = "devconf";
reg = <0x060000 0x10000>;
read-only;
};
partition@70000 {
compatible = "seama";
label = "firmware";
reg = <0x070000 0xf80000>;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
phy-mask = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "sgmii";
qca,mib-poll-interval = <500>;
qca,ar8327-initvals = <
0x04 0x00080080 /* PORT0 PAD MODE CTRL */
0x10 0x81000080 /* POWER_ON_STRAP */
0x50 0xcc35cc35 /* LED_CTRL0 */
0x54 0xcb37cb37 /* LED_CTRL1 */
0x58 0x00000000 /* LED_CTRL2 */
0x5c 0x00f3cf00 /* LED_CTRL3 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};
&eth0 {
status = "okay";
pll-data = <0x03000101 0x00000101 0x00001919>;
phy-mode = "sgmii";
phy-handle = <&phy0>;
};
&wmac {
status = "okay";
qca,no-eeprom;
};