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openwrt/target/linux/ar7/patches-2.6.32/930-titan-platform.patch
Florian Fainelli 32ec735d8a refresh 2.6.32 patches 
SVN-Revision: 23745
2010-10-31 21:45:30 +00:00

773 lines
20 KiB
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Raw Blame History

--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -131,6 +131,36 @@ static struct resource cpmac_high_res[]
},
};
+static struct resource cpmac_low_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_MAC0,
+ .end = TITAN_REGS_MAC0 + 0x7ff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 27,
+ .end = 27,
+ },
+};
+
+static struct resource cpmac_high_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_MAC1,
+ .end = TITAN_REGS_MAC1 + 0x7ff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 41,
+ .end = 41,
+ },
+};
+
static struct resource vlynq_low_res[] = {
{
.name = "regs",
@@ -185,6 +215,60 @@ static struct resource vlynq_high_res[]
},
};
+static struct resource vlynq_low_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_VLYNQ0,
+ .end = TITAN_REGS_VLYNQ0 + 0xff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 33,
+ .end = 33,
+ },
+ {
+ .name = "mem",
+ .flags = IORESOURCE_MEM,
+ .start = 0x0c000000,
+ .end = 0x0fffffff,
+ },
+ {
+ .name = "devirq",
+ .flags = IORESOURCE_IRQ,
+ .start = 80,
+ .end = 111,
+ },
+};
+
+static struct resource vlynq_high_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_VLYNQ1,
+ .end = TITAN_REGS_VLYNQ1 + 0xff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 34,
+ .end = 34,
+ },
+ {
+ .name = "mem",
+ .flags = IORESOURCE_MEM,
+ .start = 0x40000000,
+ .end = 0x43ffffff,
+ },
+ {
+ .name = "devirq",
+ .flags = IORESOURCE_IRQ,
+ .start = 112,
+ .end = 143,
+ },
+};
+
static struct resource usb_res[] = {
{
.name = "regs",
@@ -228,6 +312,18 @@ static struct plat_cpmac_data cpmac_high
.phy_mask = 0x7fffffff,
};
+static struct plat_cpmac_data cpmac_low_data_titan = {
+ .reset_bit = 17,
+ .power_bit = 20,
+ .phy_mask = 0x40000000,
+};
+
+static struct plat_cpmac_data cpmac_high_data_titan = {
+ .reset_bit = 21,
+ .power_bit = 22,
+ .phy_mask = 0x80000000,
+};
+
static struct plat_vlynq_data vlynq_low_data = {
.ops.on = vlynq_on,
.ops.off = vlynq_off,
@@ -242,6 +338,20 @@ static struct plat_vlynq_data vlynq_high
.gpio_bit = 19,
};
+static struct plat_vlynq_data vlynq_low_data_titan = {
+ .ops.on = vlynq_on,
+ .ops.off = vlynq_off,
+ .reset_bit = 15,
+ .gpio_bit = 14,
+};
+
+static struct plat_vlynq_data vlynq_high_data_titan = {
+ .ops.on = vlynq_on,
+ .ops.off = vlynq_off,
+ .reset_bit = 16,
+ .gpio_bit = 7,
+};
+
static struct platform_device physmap_flash = {
.id = 0,
.name = "physmap-flash",
@@ -275,6 +385,30 @@ static struct platform_device cpmac_high
.num_resources = ARRAY_SIZE(cpmac_high_res),
};
+static struct platform_device cpmac_low_titan = {
+ .id = 0,
+ .name = "cpmac",
+ .dev = {
+ .dma_mask = &cpmac_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &cpmac_low_data_titan,
+ },
+ .resource = cpmac_low_res_titan,
+ .num_resources = ARRAY_SIZE(cpmac_low_res_titan),
+};
+
+static struct platform_device cpmac_high_titan = {
+ .id = 1,
+ .name = "cpmac",
+ .dev = {
+ .dma_mask = &cpmac_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &cpmac_high_data_titan,
+ },
+ .resource = cpmac_high_res_titan,
+ .num_resources = ARRAY_SIZE(cpmac_high_res_titan),
+};
+
static struct platform_device vlynq_low = {
.id = 0,
.name = "vlynq",
@@ -291,6 +425,22 @@ static struct platform_device vlynq_high
.num_resources = ARRAY_SIZE(vlynq_high_res),
};
+static struct platform_device vlynq_low_titan = {
+ .id = 0,
+ .name = "vlynq",
+ .dev.platform_data = &vlynq_low_data_titan,
+ .resource = vlynq_low_res_titan,
+ .num_resources = ARRAY_SIZE(vlynq_low_res_titan),
+};
+
+static struct platform_device vlynq_high_titan = {
+ .id = 1,
+ .name = "vlynq",
+ .dev.platform_data = &vlynq_high_data_titan,
+ .resource = vlynq_high_res_titan,
+ .num_resources = ARRAY_SIZE(vlynq_high_res_titan),
+};
+
static struct gpio_led default_leds[] = {
{
@@ -300,6 +450,11 @@ static struct gpio_led default_leds[] =
},
};
+static struct gpio_led titan_leds[] = {
+ { .name = "status", .gpio = 8, .active_low = 1, },
+ { .name = "wifi", .gpio = 13, .active_low = 1, },
+};
+
static struct gpio_led dsl502t_leds[] = {
{
.name = "status",
@@ -496,6 +651,9 @@ static void __init detect_leds(void)
} else if (strstr(prid, "DG834")) {
ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
ar7_led_data.leds = dg834g_leds;
+ } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
+ ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
+ ar7_led_data.leds = titan_leds;
}
}
@@ -541,14 +699,18 @@ static int __init ar7_register_devices(v
if (res)
return res;
- ar7_device_disable(vlynq_low_data.reset_bit);
- res = platform_device_register(&vlynq_low);
+ ar7_device_disable(ar7_is_titan() ? vlynq_low_data_titan.reset_bit :
+ vlynq_low_data.reset_bit);
+ res = platform_device_register(ar7_is_titan() ? &vlynq_low_titan :
+ &vlynq_low);
if (res)
return res;
if (ar7_has_high_vlynq()) {
- ar7_device_disable(vlynq_high_data.reset_bit);
- res = platform_device_register(&vlynq_high);
+ ar7_device_disable(ar7_is_titan() ? vlynq_high_data_titan.reset_bit :
+ vlynq_high_data.reset_bit);
+ res = platform_device_register(ar7_is_titan() ? &vlynq_high_titan :
+ &vlynq_high);
if (res)
return res;
}
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -21,11 +21,11 @@
#include <asm/mach-ar7/gpio.h>
-static const char *ar7_gpio_list[AR7_GPIO_MAX];
+static const char *ar7_gpio_list[TITAN_GPIO_MAX];
int gpio_request(unsigned gpio, const char *label)
{
- if (gpio >= AR7_GPIO_MAX)
+ if (gpio >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX))
return -EINVAL;
if (ar7_gpio_list[gpio])
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -23,6 +23,9 @@
#include <asm/reboot.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
+#include <asm/mach-ar7/gpio.h>
+
+static int titan_variant;
static void ar7_machine_restart(char *command)
{
@@ -55,6 +58,18 @@ const char *get_system_type(void)
return "TI AR7 (TNETD7100)";
case AR7_CHIP_7200:
return "TI AR7 (TNETD7200)";
+ case AR7_CHIP_TITAN:
+ titan_variant = ar7_init_titan_variant();
+ switch (titan_variant /*(gpio_get_value_titan(1) >> 12) & 0xf*/) {
+ case TITAN_CHIP_1050:
+ return "TI AR7 (TNETV1050)";
+ case TITAN_CHIP_1055:
+ return "TI AR7 (TNETV1055)";
+ case TITAN_CHIP_1056:
+ return "TI AR7 (TNETV1056)";
+ case TITAN_CHIP_1060:
+ return "TI AR7 (TNETV1060)";
+ }
default:
return "TI AR7 (Unknown)";
}
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -50,6 +50,11 @@
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
+#define TITAN_REGS_MAC0 (0x08640000)
+#define TITAN_REGS_MAC1 (TITAN_REGS_MAC0 + 0x0800)
+#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
+
#define AR7_RESET_PEREPHERIAL 0x0
#define AR7_RESET_SOFTWARE 0x4
#define AR7_RESET_STATUS 0x8
@@ -59,15 +64,30 @@
#define AR7_RESET_BIT_MDIO 22
#define AR7_RESET_BIT_EPHY 26
+#define TITAN_RESET_BIT_EPHY1 28
+
/* GPIO control registers */
#define AR7_GPIO_INPUT 0x0
#define AR7_GPIO_OUTPUT 0x4
#define AR7_GPIO_DIR 0x8
#define AR7_GPIO_ENABLE 0xc
+#define TITAN_GPIO_INPUT_0 0x0
+#define TITAN_GPIO_INPUT_1 0x4
+#define TITAN_GPIO_OUTPUT_0 0x8
+#define TITAN_GPIO_OUTPUT_1 0xc
+#define TITAN_GPIO_DIR_0 0x10
+#define TITAN_GPIO_DIR_1 0x14
+#define TITAN_GPIO_ENBL_0 0x18
+#define TITAN_GPIO_ENBL_1 0x1c
#define AR7_CHIP_7100 0x18
#define AR7_CHIP_7200 0x2b
#define AR7_CHIP_7300 0x05
+#define AR7_CHIP_TITAN 0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07
/* Interrupts */
#define AR7_IRQ_UART0 15
@@ -95,14 +115,22 @@ struct plat_dsl_data {
extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
+static inline int ar7_is_titan(void)
+{
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+ AR7_CHIP_TITAN;
+}
+
static inline u16 ar7_chip_id(void)
{
- return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+ return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+ KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
}
static inline u8 ar7_chip_rev(void)
{
- return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+ 0x14))) >> 16) & 0xff;
}
static inline int ar7_cpu_freq(void)
--- a/arch/mips/include/asm/mach-ar7/gpio.h
+++ b/arch/mips/include/asm/mach-ar7/gpio.h
@@ -20,14 +20,18 @@
#define __AR7_GPIO_H__
#include <asm/mach-ar7/ar7.h>
+#ifndef __AR7_TITAN_H__
+#include <asm/mach-ar7/titan.h>
+#endif
#define AR7_GPIO_MAX 32
+#define TITAN_GPIO_MAX 51
extern int gpio_request(unsigned gpio, const char *label);
extern void gpio_free(unsigned gpio);
/* Common GPIO layer */
-static inline int gpio_get_value(unsigned gpio)
+static inline int gpio_get_value_ar7(unsigned gpio)
{
void __iomem *gpio_in =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
@@ -35,7 +39,23 @@ static inline int gpio_get_value(unsigne
return readl(gpio_in) & (1 << gpio);
}
-static inline void gpio_set_value(unsigned gpio, int value)
+static inline int gpio_get_value_titan(unsigned gpio)
+{
+ void __iomem *gpio_in0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
+ void __iomem *gpio_in1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1);
+
+ return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ return ar7_is_titan() ? gpio_get_value_titan(gpio) :
+ gpio_get_value_ar7(gpio);
+}
+
+static inline void gpio_set_value_ar7(unsigned gpio, int value)
{
void __iomem *gpio_out =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
@@ -47,7 +67,29 @@ static inline void gpio_set_value(unsign
writel(tmp, gpio_out);
}
-static inline int gpio_direction_input(unsigned gpio)
+static inline void gpio_set_value_titan(unsigned gpio, int value)
+{
+ void __iomem *gpio_out0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0);
+ void __iomem *gpio_out1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1);
+ unsigned tmp;
+
+ tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
+ if (value)
+ tmp |= 1 << (gpio & 0x1f);
+ writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ if (ar7_is_titan())
+ gpio_set_value_titan(gpio, value);
+ else
+ gpio_set_value_ar7(gpio, value);
+}
+
+static inline int gpio_direction_input_ar7(unsigned gpio)
{
void __iomem *gpio_dir =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
@@ -60,7 +102,29 @@ static inline int gpio_direction_input(u
return 0;
}
-static inline int gpio_direction_output(unsigned gpio, int value)
+static inline int gpio_direction_input_titan(unsigned gpio)
+{
+ void __iomem *gpio_dir0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
+ void __iomem *gpio_dir1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+ return 0;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+ return ar7_is_titan() ? gpio_direction_input_titan(gpio) :
+ gpio_direction_input_ar7(gpio);
+}
+
+static inline int gpio_direction_output_ar7(unsigned gpio, int value)
{
void __iomem *gpio_dir =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
@@ -74,6 +138,29 @@ static inline int gpio_direction_output(
return 0;
}
+static inline int gpio_direction_output_titan(unsigned gpio, int value)
+{
+ void __iomem *gpio_dir0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
+ void __iomem *gpio_dir1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ gpio_set_value_titan(gpio, value);
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
+ (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+ return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+ return ar7_is_titan() ? gpio_direction_output_titan(gpio, value) :
+ gpio_direction_output_ar7(gpio, value);
+}
+
static inline int gpio_to_irq(unsigned gpio)
{
return -EINVAL;
@@ -85,7 +172,7 @@ static inline int irq_to_gpio(unsigned i
}
/* Board specific GPIO functions */
-static inline int ar7_gpio_enable(unsigned gpio)
+static inline int ar7_gpio_enable_ar7(unsigned gpio)
{
void __iomem *gpio_en =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
@@ -95,7 +182,26 @@ static inline int ar7_gpio_enable(unsign
return 0;
}
-static inline int ar7_gpio_disable(unsigned gpio)
+static inline int ar7_gpio_enable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
+ void __iomem *gpio_en1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+static inline int ar7_gpio_enable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
+ ar7_gpio_enable_ar7(gpio);
+}
+
+static inline int ar7_gpio_disable_ar7(unsigned gpio)
{
void __iomem *gpio_en =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
@@ -105,6 +211,60 @@ static inline int ar7_gpio_disable(unsig
return 0;
}
+static inline int ar7_gpio_disable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
+ void __iomem *gpio_en1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+static inline int ar7_gpio_disable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
+ ar7_gpio_disable_ar7(gpio);
+}
+
+static inline int ar7_init_titan_variant(void)
+{
+ /*UINT32 new_val;*/
+ unsigned new_val;
+
+ /* set GPIO 44 - 47 as input */
+ /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */
+ /*define titan_gpio_ctrl in titan.h*/
+ titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN);
+ titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN);
+ titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN);
+ titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN);
+
+ /* read GPIO to get Titan variant type */
+ /*fix this*/
+ titan_sysGpioInValue( &new_val, 1 );
+
+ new_val >>= 12;
+ new_val &= 0x0f;
+
+ switch ( new_val )
+ {
+ case TITAN_CHIP_1050:
+ case TITAN_CHIP_1055:
+ case TITAN_CHIP_1056:
+ case TITAN_CHIP_1060:
+ return new_val;
+
+ default:
+ break;
+ }
+ /* In case we get an invalid value, return the default Titan chip */
+ return TITAN_CHIP_1050;
+}
+
#include <asm-generic/gpio.h>
#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar7/titan.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef __AR7_TITAN_H__
+#define __AR7_TITAN_H__
+
+#include <asm/mach-ar7/gpio.h>
+
+typedef enum TITAN_GPIO_PIN_MODE_tag
+{
+ FUNCTIONAL_PIN = 0,
+ GPIO_PIN = 1
+} TITAN_GPIO_PIN_MODE_T;
+
+typedef enum TITAN_GPIO_PIN_DIRECTION_tag
+{
+ GPIO_OUTPUT_PIN = 0,
+ GPIO_INPUT_PIN = 1
+} TITAN_GPIO_PIN_DIRECTION_T;
+
+/**********************************************************************
+ * GPIO Control
+ **********************************************************************/
+
+typedef struct
+{
+ int pinSelReg;
+ int shift;
+ int func;
+
+} GPIO_CFG;
+
+static GPIO_CFG gptable[]= {
+ /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
+ {4,24,1},
+ {4,26,1},
+ {4,28,1},
+ {4,30,1},
+ {5,6,1},
+ {5,8,1},
+ {5,10,1},
+ {5,12,1},
+ {7,14,3},
+ {7,16,3},
+ {7,18,3},
+ {7,20,3},
+ {7,22,3},
+ {7,26,3},
+ {7,28,3},
+ {7,30,3},
+ {8,0,3},
+ {8,2,3},
+ {8,4,3},
+ {8,10,3},
+ {8,14,3},
+ {8,16,3},
+ {8,18,3},
+ {8,20,3},
+ {9,8,3},
+ {9,10,3},
+ {9,12,3},
+ {9,14,3},
+ {9,18,3},
+ {9,20,3},
+ {9,24,3},
+ {9,26,3},
+ {9,28,3},
+ {9,30,3},
+ {10,0,3},
+ {10,2,3},
+ {10,8,3},
+ {10,10,3},
+ {10,12,3},
+ {10,14,3},
+ {13,12,3},
+ {13,14,3},
+ {13,16,3},
+ {13,18,3},
+ {13,24,3},
+ {13,26,3},
+ {13,28,3},
+ {13,30,3},
+ {14,2,3},
+ {14,6,3},
+ {14,8,3},
+ {14,12,3}
+};
+
+typedef struct
+{
+ volatile unsigned int reg[21];
+}
+PIN_SEL_REG_ARRAY_T;
+
+typedef struct
+{
+ unsigned int data_in [2];
+ unsigned int data_out[2];
+ unsigned int dir[2];
+ unsigned int enable[2];
+
+} TITAN_GPIO_CONTROL_T;
+
+#define AVALANCHE_PIN_SEL_BASE 0xA861160C /*replace with KSEG1ADDR()*/
+
+static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
+ TITAN_GPIO_PIN_DIRECTION_T pin_direction)
+{
+ int reg_index = 0;
+ int mux_status;
+ GPIO_CFG gpio_cfg;
+ volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
+ volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
+
+ if (gpio_pin > 51 )
+ return(-1);
+
+ gpio_cfg = gptable[gpio_pin];
+ mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
+ if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
+ {
+ return(-1); /* Pin have been configured for non GPIO funcs. */
+ }
+
+ /* Set the pin to be used as GPIO. */
+ pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
+
+ /* Check whether gpio refers to the first GPIO reg or second. */
+ if(gpio_pin > 31)
+ {
+ reg_index = 1;
+ gpio_pin -= 32;
+ }
+
+ if(pin_mode)
+ gpio_cntl->enable[reg_index] |= (1 << gpio_pin); /* Enable */
+ else
+ gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
+
+ if(pin_direction)
+ gpio_cntl->dir[reg_index] |= (1 << gpio_pin); /* Input */
+ else
+ gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
+
+ return(0);
+
+}/* end of function titan_gpio_ctrl */
+
+static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
+{
+ volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
+
+ if(reg_index > 1)
+ return (-1);
+
+ *in_val = gpio_cntl->data_in[reg_index];
+
+ return (0);
+}
+
+
+#endif
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